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Cypress CY14B101LA Data Retention and Endurance, Capacitance, Thermal Resistance, Preliminary

Models: CY14B101NA CY14B101LA

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Data Retention and Endurance

PRELIMINARY

CY14B101LA, CY14B101NA

Data Retention and Endurance

Parameter

Description

Min

Unit

DATAR

Data Retention

20

Years

NVC

Nonvolatile STORE Operations

200

K

Capacitance

Parameter[14]

Description

Test Conditions

Max

Unit

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

7

pF

VCC = 0 to 3.0V

COUT

Output Capacitance

7

pF

Thermal Resistance

Parameter[14]

Description

Test Conditions

48-FBGA

48-SSOP

44-TSOP II

32-SOIC

Unit

ΘJA

Thermal Resistance

Test conditions follow standard

28.82

TBD

31.11

TBD

°C/W

(Junction to Ambient)

test methods and procedures for

measuring thermal impedance,

ΘJC

Thermal Resistance

7.84

TBD

5.56

TBD

°C/W

in accordance with EIA/JESD51.

(Junction to Case)

Figure 5. AC Test Loads

	3.0V	577Ω
	3.0V	R1
		R1
	OUTPUT

30 pF

577Ω	for tri-state specs

3.0V

R1

OUTPUT

R2

5 pF

R2

789Ω

789Ω

AC Test Conditions

Input Pulse Levels	0V to 3V
Input Rise and Fall Times (10% - 90%)	<3 ns
Input and Output Timing Reference Levels	1.5V

Note

14. These parameters are guaranteed by design and are not tested.

Document #: 001-42879 Rev. *B

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Cypress CY14B101LA manual Data Retention and Endurance, Capacitance, Thermal Resistance, AC Test Conditions, Preliminary

Contents

Features Logic Block Diagram1, 2PRELIMINARY CY14B101LA, CY14B101NA Functional DescriptionPinouts 44 - TSOPTop View not to scale48-SSOP PRELIMINARYCY14B101LA, CY14B101NA Device Operation SRAM ReadSRAM Write AutoStore OperationHardware RECALL Power Up Software STORESoftware RECALL PowerPreventing AutoStore Data ProtectionNoise Considerations PRELIMINARYDC Electrical Characteristics Maximum RatingsOperating Range Ambient TemperatureData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsPRELIMINARY CY14B101LA, CY14B101NAPRELIMINARY CY14B101LA, CY14B101NA Figure 7. SRAM Read Cycle #2 CE and OE Controlled 3Figure 8. SRAM Write Cycle #1 WE Controlled 3, 18, 19 + FeedbackPRELIMINARY CY14B101LA, CY14B101NA Figure 9. SRAM Write Cycle #2 CE Controlled 3, 18, 19Figure 10. SRAM Write Cycle #3 BHE and BLE Controlled 3, 18, 19 + FeedbackAutoStore/Power Up RECALL Switching WaveformsPRELIMINARY CY14B101LA, CY14B101NASoftware Controlled STORE/RECALL Cycle Switching WaveformsPRELIMINARY CY14B101LA, CY14B101NAHardware STORE Cycle Switching WaveformsPRELIMINARY CY14B101LA, CY14B101NA Write latch setTruth Table For SRAM Operations PRELIMINARY CY14B101LA, CY14B101NACY14B101LA, CY14B101NA Ordering InformationPRELIMINARY CY14B101LA, CY14B101NA Ordering Information continuedPRELIMINARY Ordering Information continued PRELIMINARYCY14B101LA, CY14B101NA CY 14 B 101L A-ZS 20 X C T Part Numbering NomenclaturePRELIMINARY CY14B101LA, CY14B101NA Package Diagrams PRELIMINARY CY14B101LA, CY14B101NAFigure 16. 44-Pin TSOP II + FeedbackPackage Diagrams continued PRELIMINARY CY14B101LA, CY14B101NAFigure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm + FeedbackPackage Diagrams continued PRELIMINARY CY14B101LA, CY14B101NAFigure 18. 48-Pin SSOP Page 22 ofPackage Diagrams continued PRELIMINARY CY14B101LA, CY14B101NAFigure 19. 32-Pin SOIC Page 23 ofDocument History Page PRELIMINARY CY14B101LA, CY14B101NADocument Title CY14B101LA/CY14B101NA 1 Mbit 128K x 8/64K x 16 nvSRAM Document NumberSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products