PRELIMINARY CY14B101LA, CY14B101NA
Hardware STORE Cycle
Parameters |
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| Description | 20ns |
|
| 25ns |
| 45ns | Unit | |||
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| Min |
| Max | Min |
| Max | Min |
| Max | |||
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tDHSB |
| HSB | To Output Active Time when write latch not set |
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| 20 |
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| 25 |
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| 25 | ns |
tPHSB |
| Hardware STORE Pulse Width | 15 |
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| 15 |
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| 15 |
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| ns | |
tSS [29, 30] |
| Soft Sequence Processing Time |
|
| 100 |
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| 100 |
|
| 100 | μs | |
Switching Waveforms
Figure 14. Hardware STORE Cycle[23]
Write latch set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
tPHSB
tDELAY
tSTORE
tHHHD
tLZHSB
Write latch not set
tPHSB
HSB (IN)
HSB (OUT) | tDELAY |
tDHSB
HSB pin is driven high to VCC only by Internal 100kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDHSB
RWI 
Figure 15. Soft Sequence Processing[29, 30]
| Soft Sequence | tSS | Soft Sequence | tSS | ||
| Command |
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| Command |
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Address | Address #1 | Address #6 | Address #1 | Address #6 |
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| tSA |
| tCW |
| tCW |
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CE |
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VCC |
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Notes
29.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
30.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: | Page 14 of 25 |
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