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Cypress manual PRELIMINARY CY14B101LA, CY14B101NA, Package Diagrams continued, 32-Pin SOIC

Models: CY14B101NA CY14B101LA

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PRELIMINARY CY14B101LA, CY14B101NA

Package Diagrams (continued)

Figure 19. 32-Pin SOIC (51-85127)

Document #: 001-42879 Rev. *B

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Contents

Functional Description FeaturesLogic Block Diagram1, 2 PRELIMINARY CY14B101LA, CY14B101NAnot to scale Pinouts44 - TSOP Top View48-SSOP PRELIMINARYCY14B101LA, CY14B101NA AutoStore Operation Device OperationSRAM Read SRAM WritePower Hardware RECALL Power UpSoftware STORE Software RECALLPRELIMINARY Preventing AutoStoreData Protection Noise ConsiderationsAmbient Temperature DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceCY14B101LA, CY14B101NA AC Switching CharacteristicsSwitching Waveforms PRELIMINARY+ Feedback PRELIMINARY CY14B101LA, CY14B101NAFigure 7. SRAM Read Cycle #2 CE and OE Controlled 3 Figure 8. SRAM Write Cycle #1 WE Controlled 3, 18, 19+ Feedback PRELIMINARY CY14B101LA, CY14B101NAFigure 9. SRAM Write Cycle #2 CE Controlled 3, 18, 19 Figure 10. SRAM Write Cycle #3 BHE and BLE Controlled 3, 18, 19CY14B101LA, CY14B101NA AutoStore/Power Up RECALLSwitching Waveforms PRELIMINARYCY14B101LA, CY14B101NA Software Controlled STORE/RECALL CycleSwitching Waveforms PRELIMINARYWrite latch set Hardware STORE CycleSwitching Waveforms PRELIMINARY CY14B101LA, CY14B101NAPRELIMINARY CY14B101LA, CY14B101NA Truth Table For SRAM OperationsCY14B101LA, CY14B101NA Ordering InformationPRELIMINARY CY14B101LA, CY14B101NA Ordering Information continuedPRELIMINARY Ordering Information continued PRELIMINARYCY14B101LA, CY14B101NA CY 14 B 101L A-ZS 20 X C T Part Numbering NomenclaturePRELIMINARY CY14B101LA, CY14B101NA + Feedback Package DiagramsPRELIMINARY CY14B101LA, CY14B101NA Figure 16. 44-Pin TSOP II+ Feedback Package Diagrams continuedPRELIMINARY CY14B101LA, CY14B101NA Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mmPage 22 of Package Diagrams continuedPRELIMINARY CY14B101LA, CY14B101NA Figure 18. 48-Pin SSOPPage 23 of Package Diagrams continuedPRELIMINARY CY14B101LA, CY14B101NA Figure 19. 32-Pin SOICDocument Number Document History PagePRELIMINARY CY14B101LA, CY14B101NA Document Title CY14B101LA/CY14B101NA 1 Mbit 128K x 8/64K x 16 nvSRAMProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support