PRELIMINARY CY14B101LA, CY14B101NA

Document History Page

Document Title: CY14B101LA/CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM

Document Number: 001-42879

Rev.

ECN No.

Submission

Orig. of

Description of Change

 

 

Date

Change

 

 

 

 

 

 

 

**

2050747

See ECN

UNC/PYRS

New Data Sheet

*A

2607447

11/14/2008

GVCH/AESA

Removed 15 ns access speed

 

 

 

 

Updated “Features”

 

 

 

 

Updated Logic block diagram

 

 

 

 

Added footnote 1 2, 3 and 7

 

 

 

 

Pin definition: Updated WE,

HSB

and NC pin description

 

 

 

 

Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description

 

 

 

 

Updated Figure 4

 

 

 

 

Page 4: Updated Hardware store operation and Hardware RECALL (Power

 

 

 

 

up)description

 

 

 

 

Page 4: Updated Software store and software recall description

 

 

 

 

Footnote 1 and 11 referenced for Mode selection Table

 

 

 

 

Added footnote 11

 

 

 

 

Updated footnote 9 and 10

 

 

 

 

Page 6: updated Data protection description

 

 

 

 

Maximum Ratings:Added Max. Accumulated storage time

 

 

 

 

Changed Output short circuit current parameter name to DC output current

 

 

 

 

Changed ICC2 from 6mA to 10mA

 

 

 

 

Changed ICC3 from 15mA to 35mA

 

 

 

 

Changed ICC4 from 6mA to 5mA

 

 

 

 

Changed ISB from 3mA to 5mA

 

 

 

 

Added IIX for HSB

 

 

 

 

Updated ICC1, ICC3, ISB and IOZ Test conditions

 

 

 

 

Changed VCAP voltage min value from 68uF to 61uF

 

 

 

 

Added VCAP voltage max value to 180uF

 

 

 

 

Updated footnote 12 and 13

 

 

 

 

Added footnote 14

 

 

 

 

Added Data retention and Endurance Table

 

 

 

 

Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages

 

 

 

 

Updated Input Rise and Fall time in AC test Conditions

 

 

 

 

Referenced footnote 17 to tOHA parameter

 

 

 

 

Updated All switching waveforms

 

 

 

 

Updated footnote 17

 

 

 

 

Added footnote 20

 

 

 

 

 

 

 

 

Added Figure 10 (SRAM WRITE CYCLE:BHE

and BLE controlled)

 

 

 

 

Changed tSTORE max value from 12.5ms to 8ms

 

 

 

 

Updated tDELAY value

 

 

 

 

Added VHDIS, tHHHD and tLZHSB parameters

 

 

 

 

Updated footnote 24

 

 

 

 

Added footnote 26 and 27

 

 

 

 

Software controlled STORE/RECALL Table: Changed tAS to tSA

 

 

 

 

Changed tGHAX to tHA

 

 

 

 

Changed tHA value from 1ns to 0 ns

 

 

 

 

Added Figure 13

 

 

 

 

Added tDHSB parameter

 

 

 

 

Changed tHLHX to tPHSB

 

 

 

 

Updated tSS from 70us to 100us

 

 

 

 

Added truth table for SRAM operations

 

 

 

 

Updated ordering information and part numbering nomenclature

*B

2654484

02/05/09

GVCH/PYRS

Changed the data sheet from Advance information to Preliminary

 

 

 

 

Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZWE and tHZWE

 

 

 

 

Updated Figure 12

Document #: 001-42879 Rev. *B

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Cypress CY14B101LA, CY14B101NA manual Document History, Unc/Pyrs, Gvch/Aesa, Gvch/Pyrs