Cypress manual PRELIMINARY CY14B101LA, CY14B101NA, SRAM Write Cycle #2 CE Controlled 3, 18, 19

PRELIMINARY CY14B101LA, CY14B101NA

Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 21]

Address

CE

BHE, BLE

WE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 18, 19, 21]
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Document #: 001-42879 Rev. *B Page 11 of 25

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