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Cypress Preliminary, CY14B104LA, CY14B104NA, SRAM Read Cycle #2 CE and OE Controlled3, 13

Models: CY14B104LA CY14B104NA

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Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 13, 17]

PRELIMINARY

CY14B104LA, CY14B104NA

Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 13, 17]

Address

Address Valid

		tRC	tHZCE
CE		tACE
CE
		tAA
		tLZCE	t
			HZOE
OE		tDOE
OE
		tLZOE	tHZBE
BHE, BLE		tDBE
BHE, BLE
		tLZBE
Data Output	High Impedance		Output Data Valid
Data Output		tPU	Output Data Valid
		tPU	tPD
			tPD
ICC	Standby	Active

Figure 8. SRAM Write Cycle #1: WE Controlled[3, 16, 17, 18]

		tWC
Address		Address Valid
		tSCE	tHA
CE
		tBW
BHE, BLE
		tAW
		tPWE
WE		tSA
		tSA
		tSD	tHD
Data Input			Input Data Valid
		tHZWE	tLZWE
Data Output	Previous Data	High Impedance
Data Output	Previous Data

Note

18. CE or WE must be >VIH during address transitions.

Document #: 001-49918 Rev. *A

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Cypress manual Preliminary, CY14B104LA, CY14B104NA, SRAM Read Cycle #2 CE and OE Controlled3, 13, + Feedback

Contents

CY14B104LA, CY14B104NA FeaturesLogic Block Diagram1, 2 PRELIMINARYnot to scale Pinouts9 44 - TSOP 12 Top View 13 not to scalePRELIMINARY CY14B104LA, CY14B104NAPin Definitions AutoStore Operation Device OperationSRAM Read SRAM WritePRELIMINARY Hardware RECALL Power UpSoftware STORE Software RECALLPRELIMINARY Preventing AutoStoreData Protection Noise Considerations+ Feedback Best PracticesPRELIMINARY CY14B104LA, CY14B104NAPRELIMINARY DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceCY14B104LA, CY14B104NA AC Switching CharacteristicsSwitching Waveforms PRELIMINARYFigure 8. SRAM Write Cycle #1 WE Controlled3, 16 PRELIMINARYCY14B104LA, CY14B104NA Figure 7. SRAM Read Cycle #2 CE and OE Controlled3, 13Figure 10. SRAM Write Cycle #3 BHE and BLE Controlled 3, 16, 17 PRELIMINARYCY14B104LA, CY14B104NA Figure 9. SRAM Write Cycle #2 CE Controlled3, 16CY14B104LA, CY14B104NA AutoStore/Power Up RECALLSwitching Waveforms PRELIMINARYCY14B104LA, CY14B104NA Software Controlled STORE/RECALL CycleSwitching Waveforms PRELIMINARYCY14B104LA, CY14B104NA Hardware STORE CycleSwitching Waveforms PRELIMINARYPRELIMINARY For x8 ConfigurationFor x16 Configuration Truth Table For SRAM OperationsCY14B104LA, CY14B104NA Ordering InformationPRELIMINARY CY14B104LA, CY14B104NA Ordering Information continuedPRELIMINARY CY 14 B 104 L A -ZS P 20 X C T Part Numbering NomenclaturePRELIMINARY CY14B104LA, CY14B104NAFigure 16. 44-Pin TSOP II Package DiagramsPRELIMINARY CY14B104LA, CY14B104NAFigure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm Package Diagrams continuedPRELIMINARY CY14B104LA, CY14B104NAFigure 18. 54-Pin TSOP Package Diagrams continuedPRELIMINARY CY14B104LA, CY14B104NAWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Document History Page