51-85160 | Cypress CY14B104LA, CY14B104NA specification

PRELIMINARY

CY14B104LA, CY14B104NA

Figure 18. 54-Pin TSOP II (51-85160)

Document #: 001-49918 Rev. *A

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Contents

Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor Corporation 198 Champion Court X16 Top View Not to scale PinoutsTsop Pin Definitions Sram Write Device OperationSram Read AutoStore Operation A15 A07 Mode Power Hardware Recall Power UpMode Selection Software Store Data Protection Mode Selection A15 A07 PowerPreventing AutoStore Noise Considerations Best Practices Operating Range DC Electrical CharacteristicsMaximum Ratings Range Thermal Resistance Data Retention and EnduranceCapacitance AC Test Conditions AC Switching Characteristics Switching Waveforms BHE, BLE Input Data Valid High Impedance Data Input Data OutputData Input Input Data Valid High Impedance Data Output Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallHSB Software Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse Width Truth Table For Sram Operations Inputs/Outputs2 Mode PowerHSB should remain High for Sram Operations Ordering Information CY14B104LA-ZS45XIT CY14B104LA-ZS45XCTCY14B104LA-ZS45XC CY14B104LA-ZS45XI ZS Tsop Part Numbering NomenclatureCY 14 B 104 L a -ZS P 20 X C T Nvsram Package Diagrams TOP View Ball Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Sales, Solutions, and Legal InformationDocument History USB