Cypress manual CY14B104LA, CY14B104NA, Pin Definitions, Preliminary

PRELIMINARY

								CY14B104LA, CY14B104NA
Pinouts (continued)
	Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
			NC
				1		54	HSB
[5]							NC [4]
		NC		2		53
			A0	3		52	A17
			A1	4		51	A16
			A2	5		50	A15
			A3			49
				6			OE
			A4	7		48	BHE
			CE	8		47	BLE
	DQ0			9		46	DQ15
	DQ1			10	54 - TSOP II	45	DQ14
	DQ2			11	(x16)	44	DQ13
	DQ3			12		43	DQ12
	VCC			13	Top View	42	VSS
	VSS			14	(not to scale)	41	VCC
	DQ4			15		40	DQ11
	DQ5			16		39	DQ10
	DQ6			17		38	DQ9
						37
	DQ7			18			DQ8
						36
		WE		19			VCAP
						35
			A5	20			A14
						34
			A6	21			A13
						33
			A7	22			A12
						32
			A8	23			A11
						31
			A9	24			A10
						30
		NC		25			NC
		NC		26		29	NC
		NC		27		28	NC

Pin Definitions

Pin Name					I/O Type			Description
A0 – A18					Input	Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
A0 – A17						Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
DQ0 – DQ7					Input/Output	Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
						operation.
DQ0 – DQ15						Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
						operation.
					Input	Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
			WE
						address location.
					Input	Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
			CE
					Input	Output Enable, Active LOW. The active LOW				input enables the data output buffers during read
									OE
			OE
						cycles. I/O pins are tri-stated on deasserting OE HIGH.
					Input	Byte High Enable, Active LOW. Controls DQ15 - DQ8.
		BHE
					Input	Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
		BLE
		VSS			Ground	Ground for the Device. Must be connected to the ground of the system.
		VCC			Power Supply	Power Supply Inputs to the Device.
				[6]	Input/Output	Hardware Store Busy	(HSB)	. When LOW this output indicates that a hardware store is in progress.
	HSB
						When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
						up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
						is driven HIGH for short time with standard output high current.
	VCAP				Power Supply	AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
						nonvolatile elements.
			NC		No Connect	No Connect. This pin is not connected to the die.
Document #: 001-49918 Rev. *A											Page 3 of 23

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