Cypress manual Preliminary, CY14B104LA, CY14B104NA, SRAM Write Cycle #2 CE Controlled3, 16

PRELIMINARY

CY14B104LA, CY14B104NA

Figure 9. SRAM Write Cycle #2: CE Controlled[3, 16, 17, 18]

Address

CE

BHE, BLE

WE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 16, 17, 18]
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Document #: 001-49918 Rev. *A Page 12 of 23

[+] Feedback