Switching Waveforms, Read Cycle Timing18

CY7C1339G

Switching Waveforms

tCYC

CLK

tCH

tADS tADH

ADSP

ADSC

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE, BW[A:D]

ADV

Data Out (Q)

tCES tCEH

Deselect cycle

tCHZ

Q(A2)

Q(A2 + 1)

Burst wraps around to its initial state

Note:

18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05520 Rev. *F

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Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1 250 MHz 200 MHz 166 MHz 133 MHz Unit Pin ConfigurationsSelection Guide CY7C1339G Byte Write Select Inputs, active LOW. Qualified with Pin Configurations Ball BGA PinoutPin Definitions Name Description Functional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Adsp Adsc ADV Write CLK Operation Add. Used BWE BW D BW C BW B BW a Partial Truth Table for Read/Write 2Function Ambient Range Maximum RatingsOperating Range Tqfp BGA Capacitance11Thermal Resistance11 AC Test Loads and Waveforms Output Times 250 200 166 133 Parameter Description Unit Min MaxMin Max Clock Read Cycle Timing18 Switching Waveforms Write Cycle Timing18 Read/Write Cycle Timing18, 20 DON’T Care ZZ Mode Timing 22 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package Diagrams 90±0.05 Ball BGA 14 x 22 x 2.4 mm REV ECN no Issue Date Orig. Description of ChangeDocument History