Cypress CY7C1339G manual Functional Overview

			CY7C1339G
Pin Definitions (continued)
	Name	I/O	Description
		Input-	Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
	ADV
		Synchronous	automatically increments the address in a burst cycle.
		Input-	Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
	ADSP
		Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
			are also loaded into the burst counter. When ADSP and ADSC are both asserted, only	ADSP	is
			recognized. ASDP is ignored when CE1 is deasserted HIGH.
		Input-	Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
	ADSC
		Synchronous	asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
			are also loaded into the burst counter. When ADSP and ADSC are both asserted, only	ADSP	is
			recognized.
	ZZ	Input-	ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
		Asynchronous	“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
			left floating. ZZ pin has an internal pull-down.
	DQs	I/O-	Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
		Synchronous	by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
			specified by the addresses presented during the previous clock rise of the read cycle. The direction
			of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When
			HIGH, DQs are placed in a tri-state condition.
	VDD	Power Supply	Power supply inputs to the core of the device.
	VSS	Ground	Ground for the core of the device.
	VDDQ	I/O Power	Power supply for the I/O circuitry.
		Supply
	VSSQ	I/O Ground	Ground for the I/O circuitry.
	MODE	Input-	Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
		Static	floating selects interleaved burst sequence. This is a strap pin and should remain static during
			device operation. Mode Pin has an internal pull-up.
	NC,NC/9M,	–	No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M,
	NC/18M.		NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
	NC/72M,		die.
	NC/144M,
	NC/288M,
	NC/576M,
	NC/1G

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device).

The CY7C1339G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE

Document #: 38-05520 Rev. *F Page 4 of 18

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