Read/Write Cycle Timing18, 20 | Cypress CY7C1339G specs

CY7C1339G

Read/Write Cycle Timing[18, 20, 21]

Notes:

20.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

21.GW is HIGH.

A5 A6

D(A5) D(A6)

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WRITEs

Document #: 38-05520 Rev. *F

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Contents

Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor Corporation Selection Guide Pin ConfigurationsCY7C1339G 250 MHz 200 MHz 166 MHz 133 MHz Unit Pin Definitions Pin Configurations Ball BGA PinoutName Description Byte Write Select Inputs, active LOW. Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Adsp Adsc ADV Write CLK Operation Add. Used Function Partial Truth Table for Read/Write 2BWE BW D BW C BW B BW a Operating Range Maximum RatingsAmbient Range Thermal Resistance11 Capacitance11AC Test Loads and Waveforms Tqfp BGA Min Max 250 200 166 133 Parameter Description Unit Min MaxClock Output Times Read Cycle Timing18 Switching Waveforms Write Cycle Timing18 Read/Write Cycle Timing18, 20 DON’T Care ZZ Mode Timing 22 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package Diagrams 90±0.05 Ball BGA 14 x 22 x 2.4 mm Document History Issue Date Orig. Description of ChangeREV ECN no