Write Cycle Timing18 | Cypress CY7C1339G specification

CY7C1339G

Switching Waveforms (continued)

Write Cycle Timing[18, 19]

CLK

ADSP

ADSC

ADDRESS

BWE, BW[A :D]

GW

CE

ADV

OE

Data In (D)

		tCYC
	tCH	tCL
tADS	tADH
		tADS	tADH	ADSC extends burst
		tADS	tADH	tADS	tADH
				tADS	tADH
tAS	tAH
	A1			A2	A3
	Byte write signals are
	ignored for first cycle when				tWES tWEH
	ADSP initiates burst				tWES tWEH

tWES tWEH

tCES	tCEH
								tADVS tADVH
				ADV suspends burst
	tDS tDH
High-Z	D(A1)	D(A2)	D(A2 + 1)	D(A2 + 1)	D(A2 + 2)	D(A2 + 3)	D(A3)	D(A3 + 1)	D(A3 + 2)
	t
	OEHZ

Data Out (Q)

BURST READ	Single WRITE	BURST WRITE
	DON’T CARE	UNDEFINED

Note:

19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Extended BURST WRITE

Document #: 38-05520 Rev. *F

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Cypress CY7C1339G manual Write Cycle Timing18

Contents

Features Logic Block DiagramFunctional Description1 Cypress Semiconductor Corporation Pin Configurations Selection GuideCY7C1339G 250 MHz 200 MHz 166 MHz 133 MHz Unit Pin Configurations Ball BGA Pinout Pin DefinitionsName Description Byte Write Select Inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Add. Used Adsp Adsc ADV Write CLK Partial Truth Table for Read/Write 2 FunctionBWE BW D BW C BW B BW a Maximum Ratings Operating RangeAmbient Range Capacitance11 Thermal Resistance11AC Test Loads and Waveforms Tqfp BGA 250 200 166 133 Parameter Description Unit Min Max Min MaxClock Output Times Switching Waveforms Read Cycle Timing18 Write Cycle Timing18 Read/Write Cycle Timing18, 20 ZZ Mode Timing 22 DON’T Care Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm 90±0.05 Issue Date Orig. Description of Change Document HistoryREV ECN no