CY7C1339G
Document #: 38-05520 Rev. *F Page 12 of 18
Write Cycle Timing[18, 19]

Note:

19.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
BWE,
BW[A :D]
D
ata Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2)
D(A2 + 1) D(A2 + 1)
D(A1) D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
tOEHZ
tADVH
t
ADVS
tWEH
tWES
tDH
tDS
GW
tWEH
tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
[+] Feedback