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Cypress CY7C1347G Ordering Information continued, Speed, Ordering Code, Package Type, Diagram

Models: CY7C1347G

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CY7C1347G

Table 7.	Ordering Information (continued)
Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
(MHz)		Diagram		Range
250	CY7C1347G-250AXC	51-85050	100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Commercial

	CY7C1347G-250BGC	51-85115	119-Ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1347G-250BGXC		119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

	CY7C1347G-250BZC	51-85180	165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1347G-250BZXC		165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1347G-250AXI	51-85050	100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free	Industrial

	CY7C1347G-250BGI	51-85115	119-Ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1347G-250BGXI		119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

	CY7C1347G-250BZI	51-85180	165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1347G-250BZXI		165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

Document #: 38-05516 Rev. *F

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Cypress CY7C1347G manual Ordering Information continued, Speed, Ordering Code, Package Type, Operating, Diagram, Range

Contents

CY7C1347G FeaturesSelection Guide Functional Description1CY7C1347G Block Diagram+ Feedback ADDRESSCY7C1347G PinoutsCY7C1347G + FeedbackCY7C1347G Table 1. Pin Definitions CY7C1347GName DescriptionSingle Write Accesses Initiated by ADSP Single Read AccessesSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW CY7C1347GTable 5. Truth Table 2, 3, 4, 5 CY7C1347GMaximum Ratings Electrical CharacteristicsOperating Range CY7C1347GCapacitance Electrical Characteristics continuedThermal Resistance AC Test Loads and WaveformsCY7C1347G Switching CharacteristicsCY7C1347G Switching WaveformsFigure 5. Read Cycle Timing16 + FeedbackCY7C1347G Switching Waveforms continuedFigure 6. Write Cycle Timing16 + FeedbackCY7C1347G Switching Waveforms continuedFigure 7. Read/Write Cycle Timing16, 18 Page 14 of21. DQs are in high-Z when exiting ZZ sleep mode Switching Waveforms continuedCY7C1347G + FeedbackCY7C1347G Ordering InformationCY7C1347G DiagramOrdering Information continued SpeedCY7C1347G Package DiagramsFigure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm + FeedbackCY7C1347G Package Diagrams continuedFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm + FeedbackPACKAGE WEIGHT 0.475g Package Diagrams continuedCY7C1347G Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mmCY7C1347G Document History PageDocument Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document NumberPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products

Ordering Information (continued)