Selection Guide, Functional Description1 | Cypress CY7C1347G

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Cypress CY7C1347G manual Selection Guide, Functional Description1, Features, Mbit 128K x 36 Pipelined Sync SRAM

Contents

CY7C1347G FeaturesSelection Guide Functional Description1 ADDRESS Block DiagramREGISTER ADSC CY7C1347G Pinouts CY7C1347G Table 1. Pin Definitions CY7C1347GName Description Single Write Accesses Initiated by ADSP Single Read AccessesSingle Write Accesses Initiated by ADSC Functional Overview 2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Maximum Ratings Electrical CharacteristicsOperating Range VDDQ Capacitance Electrical Characteristics continuedThermal Resistance AC Test Loads and Waveforms Switching Characteristics Figure 5. Read Cycle Timing16 Switching Waveforms Figure 6. Write Cycle Timing16 Switching Waveforms continued Page 14 of Figure 7. Read/Write Cycle Timing16, 1819. GW is HIGH ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep mode Ordering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams Figure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continued Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mm PACKAGE WEIGHT 0.475gPage 20 of Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document History PageDocument Number Submission PSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products