Block Diagram, + Feedback, Address, Register

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Contents

Selection Guide FeaturesCY7C1347G Functional Description1 REGISTER Block DiagramADDRESS ADSC Pinouts CY7C1347G CY7C1347G Name CY7C1347GTable 1. Pin Definitions Description Single Write Accesses Initiated by ADSC Single Read AccessesSingle Write Accesses Initiated by ADSP Functional Overview 2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Operating Range Electrical CharacteristicsMaximum Ratings VDDQ Thermal Resistance Electrical Characteristics continuedCapacitance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Figure 5. Read Cycle Timing16 Switching Waveforms continued Figure 6. Write Cycle Timing16 19. GW is HIGH Figure 7. Read/Write Cycle Timing16, 18Page 14 of 21. DQs are in high-Z when exiting ZZ sleep mode ALL INPUTS except ZZ Ordering Information Ordering Information continued Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams continued Figure 10. 119-Ball BGA 14 x 22 x 2.4 mm Page 20 of PACKAGE WEIGHT 0.475gFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm Document Number Document History PageDocument Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Submission Worldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products

Cypress CY7C1347G manual Block Diagram, + Feedback, Address, Register, Adsc, Dq D ,Dqp D