Intel 80C186XL, 80C188XL 2.1.1Execution Unit, OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

		Address Bus (20 Bits)
General						Σ
Registers
AH	AL						Data
BH	BL
							Bus
CH	CL
							(16 Bits)
DH	DL
SP						CS
BP						DS
SI						SS
DI						ES
						IP
	ALU Data Bus				Internal
	(16 Bits)		Communications
					Registers
Temporary							Bus
Registers								External
							Control
								Bus
							Logic
ALU	EU	Instruction Queue
	Control	1	2	3	4	5	6
	System
Flags			Q Bus
			(8 Bits)
Execution Unit				Bus Interface Unit
	(EU)						(BIU)
								A1012-0A

Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU

2.1.1Execution Unit

The Execution Unit executes all instructions, provides data and addresses to the Bus Interface Unit and manipulates the general registers and the Processor Status Word. The 16-bit ALU within the Execution Unit maintains the CPU status and control flags and manipulates the general reg- isters and instruction operands. All registers and data paths in the Execution Unit are 16 bits wide for fast internal transfers.

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