Intel 80C186XL, 80C188XL End-of-Interrupt Register in Slave Mode, Used to issue the EOI command

INTERRUPT CONTROL UNIT

Register Name:				End-of-Interrupt Register (in Slave Mode)
Register Mnemonic:				EOI
Register Function:				Used to issue the EOI command
15									0
							V	V	V
							T	T	T
							2	1	0
									A1197-A0
		Bit	Bit Name	Reset		Function
	Mnemonic			State
	VT2:0		Interrupt	0	Write the three LSBs of the interrupt type (see
			Type		Table 8-5) to these bits to issue an EOI
					command in slave mode.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 8-18. End-of-Interrupt Register in Slave Mode

8.5.1.3Other Registers

The Priority Mask register is identical in Slave mode and Master mode. The Interrupt Request, Interrupt Mask, and In-Service registers retain the same function, but individual bits differ to ac- commodate the addition of the individual timer interrupts and the deletion of the external inter- rupts. Figure 8-19 shows the bit positions for Slave mode.

15

T T M M R R 2 1

DD M M A A 0 1

0

T

M

R

0

Figure 8-19. Request, Mask, and In-Service Registers

8-28