BUS INTERFACE UNIT

 

T4 T1

T2 T3

T4 T1 T2

T3 TI TI TI TI

CLKOUT

 

 

 

 

 

ALE

 

 

 

 

 

S2:0

 

Valid Status

Valid Status

AD15:0

 

Addr

 

Addr

Valid Data

[AD7:0]

 

 

 

 

 

 

 

[A15:8]

Note

 

Address

 

Address

A19:16

Note

Addr

8H

Addr

8H

BHE

Note

 

Valid

 

Valid

[RFSH=1]

 

 

 

 

 

 

 

NOTE: Drives previous bus cycle value.

A1515-0A

Figure 3-28. Returning to HALT After a DMA Bus Cycle

3.5.6Exiting HALT

An NMI or any unmasked INTn interrupt causes the BIU to exit HALT. The first bus operations to occur after exiting HALT are read cycles to reload the CS:IP registers. Figure 3-29 shows how the HALT bus state is exited when an NMI or INTn occurs.

3-32

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Image 113
Intel 80C186XL, 80C188XL user manual T4 T1 T2 T3, T3 TI TI TI TI, AD70 A158, RFSH=1, Exiting Halt