Intel 80C186XL 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEW, Chip-Selectunit, 27C256, Chip-SelectsUsing

CHIP-SELECT UNIT

27C256 74AC138

A1:13 A0:12

RD OE

A16 CS

(A)

D7:0	A19	A3	Y7	Selects 896K to 1M
	A18	A2	Y6	Selects 768K to 896K
	A17	A1	Y5

D15:8

Y4

ALE	E1	Y3
HLDA	E2	Y2
		Y1	Selects 128K to 256K
	E3	Y0	Selects 0 to 128K
		(B)

Chip-Selects Using	Chip-Selects Using
Addresses Directly	Simple Decoder

A1168-0A

Figure 6-1. Common Chip-Select Generation Methods

6.3CHIP-SELECT UNIT FUNCTIONAL OVERVIEW

The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the appropriate chip-select. Figure 6-3 illustrates the timing of a chip-select during a bus cycle. Note that the chip-select goes active in the same bus state as address goes active, eliminating any delay through address latches and decoder circuits. The Chip-Select Unit activates a chip-select for bus cycles initiated by the CPU, DMA Control Unit or Refresh Control Unit.

Six of the chip-selects map only into memory address space, while the remaining seven can map into either memory or I/O address space. The chip-selects typically associate with memory and peripheral devices as follows:

6-2