Intel 80C186XL, 80C188XL user manual 5.2POWER MANAGEMENT

CLOCK GENERATION AND POWER MANAGEMENT

X1
RES	2	5
	1
RESYNC
(Internal)
CLKOUT		1
		2
	3
RESET		6
		4

NOTES:

1.Setup of RES to falling X1.

2.RESYNC pulse generated.

3.RESYNC drives CLKOUT high, resynchronizing the clock generator.

4.RESET goes active.

5.RES allowed to go inactive after minimum 4 CLKOUT cycles.

6.RESET goes inactive 1 1/2 CLKOUT cycles after RES sampled inactive.

A1523-0A

Figure 5-8. Clock Synchronization at Reset

5.2POWER MANAGEMENT

Many VLSI devices available today use dynamic circuitry. A dynamic circuit uses a capacitor (usually parasitic gate or diffusion capacitance) to store information. The stored charge decays over time due to leakage currents in the silicon. If the device does not use the stored information before it decays, the state of the entire device may be lost. Circuits must periodically refresh dy- namic RAMs, for example, to ensure data retention. Any microprocessor that has a minimum clock frequency has dynamic logic. On a dynamic microprocessor, if you stop or slow the clock, the dynamic nodes within it begin discharging. With a long enough delay, the processor is likely to lose its present state, needing a reset to resume normal operation.

An 80C186 Modular Core microprocessor is fully static. The CPU stores its current state in flip-flops, not capacitive nodes. The clock signal to both the CPU core and the peripherals can stop without losing any internal information, provided the design maintains power. When the clock restarts, the device will execute from its previous state. When the processor is inactive for significant periods, special power management hardware takes advantage of static operation to achieve major power savings.

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