Intel 80C186XL, 80C188XL user manual Figures

CONTENTS

FIGURES

Figure		Page
2-1	Simplified Functional Block Diagram of the 80C186 Family CPU	................................2-2
2-2	Physical Address Generation	2-3
2-3	General Registers	2-4
2-4	Segment Registers	2-6
2-5	Processor Status Word	2-9
2-6	Segment Locations in Physical Memory	2-10
2-7	Currently Addressable Segments	2-11
2-8	Logical and Physical Address	2-12
2-9	Dynamic Code Relocation	2-14
2-10	Stack Operation	2-16
2-11	Flag Storage Format	2-19
2-12	Memory Address Computation	2-29
2-13	Direct Addressing	2-30
2-14	Register Indirect Addressing	2-31
2-15	Based Addressing	2-31
2-16	Accessing a Structure with Based Addressing	2-32
2-17	Indexed Addressing	2-33
2-18	Accessing an Array with Indexed Addressing	2-33
2-19	Based Index Addressing	2-34
2-20	Accessing a Stacked Array with Based Index Addressing	2-35
2-21	String Operand	2-36
2-22	I/O Port Addressing	2-36
2-23	80C186 Modular Core Family Supported Data Types	2-38
2-24	Interrupt Control Unit	2-39
2-25	Interrupt Vector Table	2-40
2-26	Interrupt Sequence	2-42
2-27	Interrupt Response Factors	2-46
2-28	Simultaneous NMI and Exception	2-47
2-29	Simultaneous NMI and Single Step Interrupts	2-48
2-30	Simultaneous NMI, Single Step and Maskable Interrupt	2-49
3-1	Physical Data Bus Models	3-2
3-2	16-Bit Data Bus Byte Transfers	3-3
3-3	16-Bit Data Bus Even Word Transfers	3-4
3-4	16-Bit Data Bus Odd Word Transfers	3-5
3-5	8-Bit Data Bus Word Transfers	3-6
3-6	Typical Bus Cycle	3-8
3-7	T-State Relation to CLKOUT	3-8
3-8	BIU State Diagram	3-9
3-9	T-State and Bus Phases	3-10
3-10	Address/Status Phase Signal Relationships	3-11
3-11	Demultiplexing Address Information	3-12
3-12	Data Phase Signal Relationships	3-14
3-13	Typical Bus Cycle with Wait States	3-15
3-14	ARDY and SRDY Pin Block Diagram	3-15

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