Intel 80C186XL 8.4.8Interrupt Status Register, Register Name Register Mnemonic Register Function

INTERRUPT CONTROL UNIT

Register Name:

Register Mnemonic:

Register Function:

15

N

S

P

E

C

End-of-Interrupt Register

EOI

Used to issue an EOI command

				0
V	V	V	V	V
T	T	T	T	T
4	3	2	1	0

A1210-A0

Bit	Bit Name	Reset	Function
Mnemonic		State
NSPEC	Nonspecific	0	Set to issue a nonspecific EOI.
	EOI
VT4:0	Interrupt	0 0000	Write with the interrupt type of the interrupt
	Type		whose In-Service bit is to be cleared.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 8-13. End-of-Interrupt Register

8.4.8Interrupt Status Register

The Interrupt Status register (Figure 8-14) contains the DMA Halt bit and one bit for each timer interrupt. The CPU sets the DMA Halt bit to suspend DMA transfers while an NMI is processed. Software can also read and write this bit. See “Suspension of DMA Transfers” on page 10-20 for details. A timer bit is set to indicate a pending interrupt and is cleared when the interrupt request is acknowledged. Any number of bits can be set at any one time.

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