Intel 80C188XL, 80C186XL user manual Register Name, Register Mnemonic, PSW Flags, Register Function

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Register Name:			Processor Status Word
Register Mnemonic:			PSW (FLAGS)
Register Function:			Posts CPU status information.
15
	O	D	I	T	S	Z	A	P
	F	F	F	F	F	F	F	F

0

C

F

A1035-0A

Bit	Bit Name	Reset	Function
Mnemonic		State
OF	Overflow Flag	0	If OF is set, an arithmetic overflow has occurred.
			If DF is set, string instructions are processed high
DF	Direction Flag	0	address to low address. If DF is clear, strings are
			processed low address to high address.
	Interrupt		If IF is set, the CPU recognizes maskable interrupt
IF		0	requests. If IF is clear, maskable interrupts are
	Enable Flag
			ignored.
TF	Trap Flag	0	If TF is set, the processor enters single-step mode.
SF	Sign Flag	0	If SF is set, the high-order bit of the result of an
			operation is 1, indicating it is negative.
ZF	Zero Flag	0	If ZF is set, the result of an operation is zero.
			If AF is set, there has been a carry from the low
AF	Auxiliary Flag	0	nibble to the high or a borrow from the high nibble
			to the low nibble of an 8-bit quantity. Used in BCD
			operations.
PF	Parity Flag	0	If PF is set, the result of an operation has even
			parity.
			If CF is set, there has been a carry out of, or a
CF	Carry Flag	0	borrow into, the high-order bit of the result of an
			instruction.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 2-5. Processor Status Word

2-9