Intel 80C188XL Register Name, DMA Control Register, Register Mnemonic, DxCON, Register Function

	DIRECT MEMORY ACCESS UNIT
Register Name:	DMA Control Register
Register Mnemonic:	DxCON
Register Function:	Controls DMA channel parameters.

15

D	D	D	S
M	D	I	M
E	E	N	E
M	C	C	M

SS D I E N C C

TI C N T

S	S	P	I
Y	Y		D
N	N		R
1	0		Q

		0
C	S	W
H	T	O
G	R	R
	T	D

A1180-0A

Bit	Bit Name	Reset	Function
Mnemonic		State
CHG	Change	X	Set CHG to enable modifying the STRT bit.
	Start Bit
STRT	Start DMA	0	Set STRT to arm the DMA channel. The STRT bit can
	Channel		be modified only when the CHG bit is set.
WORD	Word	X	Set WORD to select word transfers; clear WORD to
	Transfer		select byte transfers. The 8-bit bus versions of the
	Select		device ignore the WORD bit.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 10-11. DMA Control Register (Continued)

10.2.1.3Selecting the Source of DMA Requests

DMA requests can come from either an internal source (Timer 2) or an external source.

Internal DMA requests are selected by setting the IDRQ bit in the DMA Control Register (see Figure 10-11 on page 10-15) for the channel. The DMA channel ignores its DRQ pin when inter- nal requests are programmed. Similarly, the DMA channel responds only to the DRQ pin (and ignores internal requests) when external requests are selected.

10-17