Intel 80C188XL, 80C186XL Mpcs, Register Mnemonic, Chip-Selectunit, 9.MPCS Register Definition

CHIP-SELECT UNIT

Register Name:MCS and PCS Alternate Control Register

Register Mnemonic: MPCS

Register Function:Controls operation of the MCS and PCS chip- selects.

15

M	M	M
6	5	4

MM

3 2

MM

1 0

EM X S

		0
R	R	R
2	1	0

A1144-0A

Bit

Bit Name

Reset

Function

Mnemonic

State

M6:0

Block Size

XXH

Defines the block size for the MCS chip-selects.

Table 6-5 on page 6-14 lists allowable values.

EX

Pin Selector

XH

Setting EX configures

as chip-selects.

PCS6:5

Clearing EX configures the pins as latched

address bits A2:A1.

MS

Bus Cycle

XH

Clearing MS activates

for I/O bus

PCS6:0

Selector

cycles. Setting MS activates

PCS6:0

for

memory bus cycles.

R2

Bus Ready

X

Applies only to

When R2 is clear, bus

PCS6:4.

Disable for

ready must be active to complete a bus cycle.

PCS6:4

When R2 is set, R1:0 control the number of bus

wait states and bus ready is ignored.

R1:0

Wait State

3H

Apply only to

R1:0 define the minimum

PCS6:4.

Value for

number of wait states inserted into the bus

PCS6:4

cycle.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A starting address other than an integer multiple of the block size defined in this register causes unreliable chip-select operation. Reading this register and the MMCS or PACS register (before writing them) enables the associated chip-selects; however, none of the programmable fields will be properly initialized.

Figure 6-9. MPCS Register Definition

6-11