Intel 80C188XL, 80C186XL MCS Control Register, Mmcs, Controls the operation Chip-selects, Mcs

CHIP-SELECT UNIT

Register Name:
	MCS Control Register
Register Mnemonic:	MMCS
Register Function:	Controls the operation of the		chip-selects.
		MCS

15

U	U	U	U
1	1	1	1
9	8	7	6

U U

11

54

U

1

3

		0
R	R	R
2	1	0

						A1143-0B
Bit	Bit Name	Reset				Function
Mnemonic		State
U19:13	Start	XXH	Defines the starting address for the block of
	Address		MCS		chip-selects. During memory bus cycles,
			U19:13 are compared with the A19:13 address
			bits. An equal to or greater than result enables
			the	MCS		chip-select. The starting address must
			be an integer multiple of the block size defined
			in the MPCS register. See Table 6-5 on page
			6-14 for additional information.
R2	Bus Ready	X	When R2 is clear, bus ready must be active to
	Disable		complete a bus cycle. When R2 is set, R1:0
			control the number of bus wait states and bus
			ready is ignored.
R1:0	Wait State	3H	R1:0 define the minimum number of wait states
	Value		inserted into the bus cycle.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A starting address other than an integer multiple of the block size defined in the MPCS register causes unreliable chip-select operation. (See Table 6-5 on page 6-14 for details.) Reading this register and the MPCS register (before writing them) enables the MCS chip-selects; however, none of the programmable fields will be properly ini- tialized.

Figure 6-7. MMCS Register Definition

6-9