Intel 80C186XL Instruction Set Opcodes And Clock Cycles, BIT MANIPULATION INSTRUCTIONS Continued

INSTRUCTION SET OPCODES AND CLOCK CYCLES

Table D-2. Instruction Set Summary (Continued)

Function		Format			Clocks	Notes
BIT MANIPULATION INSTRUCTIONS (Continued)
TEST= And function to flags, no result
register/memory and register	1 0 0 0 0 1 0 w	mod reg r/m			3/10
immediate data and register/memory
	1 1 1 1 0 1 1 w	mod 000 r/m	data	data if w=1	4/10
immediate data and accumulator
	1 0 1 0 1 0 0 w	data	data if w=1		3/4	(1)
Shifts/Rotates
register/memory by 1	1 1 0 1 0 0 0 w	mod TTT r/m			2/15
register/memory by CL
	1 1 0 1 0 0 1 w	mod TTT r/m			5+n/17+n
register/memory by Count	1 1 0 0 0 0 0 w	mod TTT r/m	count		5+n/17+n
STRING MANIPULATION INSTRUCTIONS
MOVS = Move byte/word	1 0 1 0 0 1 0 w				14
INS = Input byte/word from DX port	0 1 1 0 1 1 0 w				14
OUTS = Output byte/word to DX port	0 1 1 0 1 1 1 w				14
CMPS = Compare byte/word	1 0 1 0 0 1 1 w				22
SCAS = Scan byte/word
	1 0 1 0 1 1 1 w				15
STRING MANIPULATION INSTRUCTIONS (Continued)
LODS = Load byte/word to AL/AX	1 0 1 0 1 1 0 w				12
STOS = Store byte/word from AL/AX
	1 0 1 0 1 0 1 w				10
Repeated by count in CX:
MOVS = Move byte/word	1 1 1 1 0 0 1 0	1 0 1 0 0 1 0 w			8+8n
INS = Input byte/word from DX port	1 1 1 1 0 0 1 0	0 1 1 0 1 1 0 w			8-8n
OUTS = Output byte/word to DX port	1 1 1 1 0 0 1 0	0 1 1 0 1 1 1 w			8+8n
CMPS = Compare byte/word	1 1 1 1 0 0 1 z	1 0 1 0 0 1 1 w			5+22n
SCAS = Scan byte/word	1 1 1 1 0 0 1 z	1 0 1 0 1 1 1 w			5+15n
LODS = Load byte/word to AL/AX	1 1 1 1 0 0 1 0	0 1 0 1 0 0 1 w			6+11n
STOS = Store byte/word from AL/AX	1 1 1 1 0 1 0 0	0 1 0 1 0 0 1 w			6+9n

NOTES:

1.Clock cycles are given for 8-bit/16-bit operations.

2.Clock cycles are given for jump not taken/jump taken.

3.Clock cycles are given for interrupt taken/interrupt not taken.

4.If TEST = 0

Shading indicates additions and enhancements to the 8086/8088 instruction set. See Appendix A, “80C186 Instruction Set Additions and Extensions,” for details.

D-6