Intel 80C186XL, 80C188XL user manual Figures, Contents, Page, 6-11

CONTENTS

FIGURES

Figure		Page
6-11	Wait State and Ready Control Functions	6-16
6-12	Using Chip-Selects During HOLD	6-18
6-13	Typical System	6-19
7-1	Refresh Control Unit Block Diagram	7-1
7-2	Refresh Control Unit Operation Flow Chart	7-3
7-3	Refresh Address Formation	7-4
7-4	Suggested DRAM Control Signal Timing Relationships	7-6
7-5	Formula for Calculating Refresh Interval for RFTIME Register	7-7
7-6	Refresh Base Address Register	7-8
7-7	Refresh Clock Interval Register	7-9
7-8	Refresh Control Register	7-10
7-9	Regaining Bus Control to Run a DRAM Refresh Bus Cycle	7-13
8-1	Interrupt Control Unit in Master Mode	8-2
8-2	Using External 8259A Modules in Cascade Mode	8-8
8-3	Interrupt Control Unit Latency and Response Time	8-11
8-4	Interrupt Control Register for Internal Sources	8-13
8-5	Interrupt Control Register for Noncascadable External Pins	8-14
8-6	Interrupt Control Register for Cascadable Interrupt Pins	8-15
8-7	Interrupt Request Register	8-16
8-8	Interrupt Mask Register	8-17
8-9	Priority Mask Register	8-18
8-10	In-Service Register	8-19
8-11	Poll Register	8-20
8-12	Poll Status Register	8-21
8-13	End-of-Interrupt Register	8-22
8-14	Interrupt Status Register	8-23
8-15	Interrupt Control Unit in Slave Mode	8-24
8-16	Interrupt Sources in Slave Mode	8-25
8-17	Interrupt Vector Register (Slave Mode Only)	8-27
8-18	End-of-Interrupt Register in Slave Mode	8-28
8-19	Request, Mask, and In-Service Registers	8-28
8-20	Interrupt Vectoring in Slave Mode	8-29
8-21	Interrupt Response Time in Slave Mode	8-30
9-1	Timer/Counter Unit Block Diagram	9-2
9-2	Counter Element Multiplexing and Timer Input Synchronization	9-3
9-3	Timers 0 and 1 Flow Chart	9-4
9-4	Timer/Counter Unit Output Modes	9-6
9-5	Timer 0 and Timer 1 Control Registers	9-7
9-6	Timer 2 Control Register	9-9
9-7	Timer Count Registers	9-10
9-8	Timer Maxcount Compare Registers	9-11
9-9	TxOUT Signal Timing	9-15
10-1	Typical DMA Transfer	10-2
10-2	DMA Request Minimum Response Time	10-4

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