Intel 80C186XL, 80C188XL user manual Ucs, AD70 O0-7, 27C256, LA151 AD158, Write Bus Cycles

BUS INTERFACE UNIT

3.5.1.1Refresh Bus Cycles

A refresh bus cycle operates similarly to a normal read bus cycle except for the following:

•For a 16-bit data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the bus is ignored.

•For an 8-bit data bus, address bit A0 drives to a 1 (high) and RFSH is driven active (low). The data value on the bus is ignored. RFSH has the same bus timing as BHE.

UCS	CE
AD7:0	O0-7
	27C256
LA15:1	A 0-14
RD	OE
	OE
	A 0-14
AD15:8	27C256
	O0-7
	CE

Note: A0 and BHE are not used.

A1105-0A

Figure 3-20. Read-Only Device Interface

3.5.2Write Bus Cycles

Figure 3-21 illustrates a typical write bus cycle. The bus cycle starts with the transition of ALE high and the generation of valid status bits S2:0. The bus cycle ends when WR transitions high (inactive), although data remains valid for one additional clock. Table 3-4 lists the two types of write bus cycles.

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