Intel 80C186XL, 80C188XL user manual Poll Register, Ireq

INTERRUPT CONTROL UNIT

Reading the Poll register (Figure 8-11) acknowledges the pending interrupt, just as if the CPU had started the interrupt vectoring sequence. The Interrupt Control Unit updates the Interrupt Re- quest, In-Service, Poll, and Poll Status registers, as it does in the normal interrupt acknowledge sequence. However, the processor does not run an interrupt acknowledge sequence or fetch the vector from the vector table. Instead, software must read the interrupt type and execute the proper routine to service the pending interrupt.

Reading the Poll Status register (Figure 8-12) will merely transmit the status of the polling bits without modifying any of the other Interrupt Controller registers.

Register Name:

Register Mnemonic:

Register Function:

15

I

R

E

Q

Poll Register

POLL

Read to check for and acknowledge pending interrupts when polling

				0
V	V	V	V	V
T	T	T	T	T
4	3	2	1	0

			A1208-A0
Bit	Bit Name	Reset	Function
Mnemonic		State
IREQ	Interrupt	0	This bit is set to indicate a pending interrupt.
	Request
VT4:0	Vector Type	0	Contains the interrupt type of the highest
			priority pending interrupt.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 8-11. Poll Register

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