Intel 80C186XL, 80C188XL Interrupt Response Time, Clocks, Total, Interrupt and Exception Priority

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.3.4Interrupt Response Time

Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction in the service routine is executed. Interrupt response time is less for interrupts or exceptions which supply their own vector type. The maskable interrupt has a longer response time because the vector type must be supplied by the Interrupt Control Unit (see Chapter 8, “Interrupt Control Unit”).

Figure 2-27 shows the events that dictate interrupt response time for the interrupts that supply their type. Note that an on-chip bus master, such as the DRAM Refresh Unit, can make use of idle bus cycles. This can increase interrupt response time.

	Clocks
Idle	5
Read IP	4
Idle	5
Read CS	4
Idle	4
Push Flags	4
Idle	3
Push CS	4
Push IP	4
Idle	5

First Instruction Fetch

From Interrupt Routine

Total 42

A1030-0A

Figure 2-27. Interrupt Response Factors

2.3.5Interrupt and Exception Priority

Interrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable in- terrupt are both recognized on the same instruction boundary, NMI has precedence. The maskable interrupt will not be recognized until the Interrupt Enable bit is set and it is the highest priority.

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