Intel 80C186XL, 80C188XL user manual Trap Flag = ???, Simultaneous NMI and Single Step Interrupts

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruc- tion boundary as a single step, the interrupt vector is taken first, then is followed immediately by the single step vector. However, the single step service routine is executed before the interrupt service routine (see Figure 2-29). If the single step service routine re-enables single step by exe- cuting the IRET, the interrupt service routine will also be single stepped. This can severely limit the real-time response of the CPU to an interrupt.

To prevent the single-step routine from executing before a maskable interrupt, disable interrupts while single stepping an instruction, then enable interrupts in the single step service routine. The maskable interrupt is serviced from within the single step service routine and that interrupt ser- vice routine is not single-stepped. To prevent single stepping before an NMI, the single-step ser- vice routine must compare the return address on the stack to the NMI vector. If they are the same, return to the NMI service routine immediately without executing the single step service routine.

NMI Instruction

Trap Flag = 1

Push PSW, CS, IP

Fetch Divide Error Vector

Trap Flag = 0

Push PSW, CS, IP

Fetch Single Step Vector

Execute Single Step

Service Routine

IRET

Trap Flag = ???

A1032-0A

Figure 2-29. Simultaneous NMI and Single Step Interrupts

The most complicated case is when an NMI, a maskable interrupt, a single step and another ex- ception are pending on the same instruction boundary. Figure 2-30 shows how this case is prior- itized by the CPU. Note that if the single-step routine sets the Trap Flag (TF) bit before executing the IRET instruction, the NMI routine will also be single stepped.

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