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Intel 80C186XL, 80C188XL NMI Instruction, Trap Flag =, Push PSW, CS, IP Fetch Divide Error Vector

Models: 80C186XL 80C188XL

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NMI Instruction

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruc- tion boundary as a single step, the interrupt vector is taken first, then is followed immediately by the single step vector. However, the single step service routine is executed before the interrupt service routine (see Figure 2-29). If the single step service routine re-enables single step by exe- cuting the IRET, the interrupt service routine will also be single stepped. This can severely limit the real-time response of the CPU to an interrupt.

To prevent the single-step routine from executing before a maskable interrupt, disable interrupts while single stepping an instruction, then enable interrupts in the single step service routine. The maskable interrupt is serviced from within the single step service routine and that interrupt ser- vice routine is not single-stepped. To prevent single stepping before an NMI, the single-step ser- vice routine must compare the return address on the stack to the NMI vector. If they are the same, return to the NMI service routine immediately without executing the single step service routine.

NMI Instruction

Trap Flag = 1

Push PSW, CS, IP

Fetch Divide Error Vector

Trap Flag = 0

Push PSW, CS, IP

Fetch Single Step Vector

Execute Single Step

Service Routine

IRET

Trap Flag = ???

A1032-0A

Figure 2-29. Simultaneous NMI and Single Step Interrupts

The most complicated case is when an NMI, a maskable interrupt, a single step and another ex- ception are pending on the same instruction boundary. Figure 2-30 shows how this case is prior- itized by the CPU. Note that if the single-step routine sets the Trap Flag (TF) bit before executing the IRET instruction, the NMI routine will also be single stepped.

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Intel 80C186XL, 80C188XL NMI Instruction, Push PSW, CS, IP Fetch Divide Error Vector, Trap Flag = Push PSW, CS, IP

Contents

80C186XL/80C188XL Microprocessor User’s Manual 1995 80C186XL/80C188XL Microprocessor User’s ManualIntel Corporation Literature Sales P.O. Box CHAPTER CONTENTSINTRODUCTION CHAPTERBUS INTERFACE UNIT CONTENTSCHAPTER CLOCK GENERATION AND POWER MANAGEMENT CONTENTSCHAPTER PERIPHERAL CONTROL BLOCKCHAPTER CONTENTSREFRESH CONTROL UNIT CHAPTERTIMER/COUNTER UNIT CONTENTSDIRECT MEMORY ACCESS UNIT CHAPTERMATH COPROCESSING CONTENTSCHAPTER ONCE MODE CONTENTSCHAPTER APPENDIX ACONTENTS FIGURESFigure PageFIGURES CONTENTSFigure PageFIGURES CONTENTSFigure PageFIGURES CONTENTSFigure PageCONTENTS TABLESTable PageTABLES CONTENTSTable PageCONTENTS EXAMPLESExample PageIntroduction Page CHAPTER INTRODUCTION INTRODUCTION 1.1HOW TO USE THIS MANUALTable 1-2.Related Documents and Software 1.2RELATED DOCUMENTSINTRODUCTION 1.3ELECTRONIC SUPPORT SYSTEMS 1.3.1FaxBack Service1.3.2Bulletin Board System BBS 1.4TECHNICAL SUPPORT 1.3.3CompuServe Forums1.3.4World Wide Web 1.6TRAINING CLASSES 1.5PRODUCT LITERATUREPage Overview of the 80C186 Family Architecture Page 2.1ARCHITECTURAL OVERVIEW CHAPTER OVERVIEW OF THE 80C186 FAMILYARCHITECTURE OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.1Execution Unit2.1.2Bus Interface Unit Figure 2-3.General Registers 2.1.3General RegistersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-1.Implicit Use of General Registers 2.1.4Segment RegistersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-4.Segment Registers 2.1.5Instruction PointerOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.6Flags 2.1.7Memory Segmentation Register Mnemonic Register NameRegister Function Reset2.1.8Logical Addresses B E H J Data: DS Code: CS Stack: SS Extra: ESFFFFFH A B D E G J K 0H C F H IAddresses Segment Base Physical Address Offset 3H Segment Base LogicalOffset 13H 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBHTable 2-2.Logical Address Sources 2.1.9Dynamically Relocatable CodeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before 2.1.11 Reserved Memory and I/O Space 2.1.10 Stack ImplementationFigure 2-10.Stack Operation OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1Instruction Set 2.2SOFTWARE OVERVIEW2.2.1.1Data Transfer Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-3.Data Transfer Instructions General-PurposeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE I = Interrupt Enable Flag T = Trap FlagFigure 2-11.Flag Storage Format 2.2.1.2Arithmetic InstructionsTable 2-4.Arithmetic Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREAddition Subtraction2.2.1.3Bit Manipulation Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-6.Bit Manipulation Instructions Bit PatternTable 2-7.String Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.4String Instructions 2.2.1.5Program Transfer Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURESI DI CX AL/AX DF ZF Scan value Destination for LODS Source for STOSUnconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers Table 2-9.Program Transfer Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREConditional Transfers Unconditional TransfersMnemonic OVERVIEW OF THE 80C186 FAMILY ARCHITECTURECondition Tested “Jump if…”OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2Addressing Modes2.2.1.6Processor Control Instructions Table 2-11.Processor Control Instructions2.2.2.2Memory Addressing Modes OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREEncoded in the Instruction Explicit in the Opcode DisplacementMod R/M OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREOpcode DisplacementMod R/M BX or BPDisplacement Opcode Opcode DisplacementMod R/M BX or BPHigh Address Source EA Destination EA Opcode SI DIOpcode Data Port Address Direct Port AddressingTable 2-12.Supported Data Types OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREType DescriptionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Maskable Interrupt Request Interrupt Acknowledge NMI CPUInterrupt Control Unit External Interrupt SourcesFigure 2-25.Interrupt Vector Table OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE3.The current CS and IP are pushed onto the stack Stack PSW Single Step — Type Divide Error — TypeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.1.2Maskable InterruptsBreakpoint Interrupt — Type Numerics Coprocessor Fault — TypeInterrupt on Overflow — Type Array Bounds Check — Type2.3.3Interrupt Latency 2.3.2Software InterruptsClocks 2.3.4Interrupt Response TimeTotal 2.3.5Interrupt and Exception PriorityPush PSW, CS, IP Fetch Divide Error Vector Divide ErrorService Routine IRET Execute Divide Service Routine IRETService Routine IRET Trap Flag = ??? Push PSW, CS, IP Fetch Divide Error VectorNMI Instruction Trap Flag =Interrupt Enable Bit IE = Trap Flag TF = Page Bus Interface Unit Page 3.1MULTIPLEXED ADDRESS AND DATA BUS CHAPTER BUS INTERFACE UNIT3.2ADDRESS AND DATA BUS CONCEPTS 3.2.116-BitData Bus512 KBytes 1 MByte512 KBytes Odd Byte Transfer Even Byte TransferD15:8 BHE A19:1D7:0 A0 Low BUS INTERFACE UNIT3.2.28-BitData Bus First Bus CycleSecond Bus Cycle D7:0 A19:03.3MEMORY AND I/O INTERFACES First Bus Cycle3.4BUS CYCLE OPERATION 3.3.116-BitBus Memory and I/O Requirements3.3.28-BitBus Memory and I/O Requirements CLKOUT PhaseFalling RisingBus Ready 3.4.1Address/Status Phase or TI Signals From CPU 3.4.3Wait States 3.4.2Data Phaseor TW T1 T2 T3 TW TW T4 CLKOUT Wait State Module Input Input CS1 CS2 CS3 CS4 ALE CLKOUTClear Clock READYLoad Wait State Module CS1 Enable CS2READY CLKOUTARDY SRDY 3.4.4Idle StatesCLKOUT •The instruction prefetch queue is full 3.5.1Read Bus Cycles 3.5BUS CYCLESBUS INTERFACE UNIT Table 3-2. Read Bus Cycle TypesCLKOUT 27C256 27C2563.5.2Write Bus Cycles CLKOUT A0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WE LA15:1 RD LA0 WR BHEAD7:0 AD15:8 BUS INTERFACE UNITTable 3-5.Write Cycle Critical Timing Parameters 3.5.3Interrupt Acknowledge Bus CycleBUS INTERFACE UNIT DT/R DEN A19:16 A15:8 BHE RD, WR CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCKT1 T2 T3 T4Processor 3.5.4HALT Bus Cycle CLKOUT CONTROL 3.5.5Temporarily Exiting the HALT Bus StateCLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16 BUS INTERFACE UNIT CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHERFSH 3.5.6Exiting HALT CLKOUT 3.6SYSTEM DESIGN ALTERNATIVESNMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE RFSH3.6.1Buffering the Data Bus A19:16 3.6.2Synchronizing Software and Hardware Events 3.6.3Using a Locked Bus BUS INTERFACE UNIT 3.6.4Using the Queue Status SignalsTable 3-7.Queue Status Signal Decoding 3.7.1Entering Bus HOLD 3.7MULTI-MASTERBUS SYSTEM DESIGNSBUS INTERFACE UNIT Figure 3-33.Queue Status TimingCLKOUT 3.7.1.2Refresh Operation During a Bus HOLD BUS INTERFACE UNITCLKOUT +5 HLDA RESET HOLD 3.7.2Exiting HOLDPRE DQ CLR Latched HLDA3.8BUS CYCLE PRIORITIES 9.DMA bus cycles Page Peripheral Control Block Page 4.2PCB RELOCATION REGISTER CHAPTER PERIPHERAL CONTROL BLOCK4.1PERIPHERAL CONTROL REGISTERS RELREG PCB Relocation RegisterRelocates the PCB within memory or I/O space Register NameTable 4-1.Peripheral Control Block PERIPHERAL CONTROL BLOCKFunction Function4.4.2READY Signals and Wait States 4.4ACCESSING THE PERIPHERAL CONTROL BLOCK4.3RESERVED LOCATIONS 4.4.1Bus CyclesWord reads 4.4.3F-BusOperationaddress Byte reads4.4.3.2Accessing the Peripheral Control Registers 4.5SETTING THE PCB BASE LOCATION4.4.3.3Accessing Reserved Locations PERIPHERAL CONTROL BLOCKPage Page Clock Generation and Power Management Page 5.1.1Crystal Oscillator CHAPTER CLOCK GENERATION AND POWER MANAGEMENT5.1CLOCK GENERATION Z0 = Inverter Output Z CLOCK GENERATION AND POWER MANAGEMENT180˚ 5.1.1.1Oscillator OperationFundamental Figure 5-4.Equations for Crystal Calculations CLOCK GENERATION AND POWER MANAGEMENTCLKOUT Third-OvertoneCrystal5.1.1.2Selecting Crystals CLOCK GENERATION AND POWER MANAGEMENT5.1.3Output from the Clock Generator 5.1.2Using an External Oscillator5.1.4Reset and Clock Synchronization CLOCK GENERATION AND POWER MANAGEMENT RESET IN 1µf typicalFigure 5-5.Simple RC Circuit for Powerup Reset 50 k typicalRESET CLOCK GENERATION AND POWER MANAGEMENTFigure 5-6.Cold Reset Waveform X1 VccFigure 5-7.Warm Reset Waveform CLOCK GENERATION AND POWER MANAGEMENT5.2POWER MANAGEMENT 5.2.1.1Entering Power-SaveMode 5.2.1Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Power Save Register PWRSAV Register Name Register Mnemonic Register FunctionEnables and sets clock division factor 0 F F 1 CLOCK GENERATION AND POWER MANAGEMENTCLOCK GENERATION AND POWER MANAGEMENT CLKOUT WRFigure 5-10. Power-SaveClock Transition 5.2.1.2Leaving Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Chip-SelectUnit Page 6.1COMMON METHODS FOR GENERATING CHIP-SELECTS 6.2CHIP-SELECTUNIT FEATURES AND BENEFITSCHAPTER CHIP-SELECTUNIT Chip-SelectsUsing 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEWChip-SelectsUsing CHIP-SELECTUNITInternal device EPROM or Flash memory types 1.The chip-selectis enabled 6.4.1Initialization Sequence 6.4PROGRAMMINGRegister Mnemonic Register NameRegister Function CHIP-SELECTUNITRegister Mnemonic Register NameRegister Function CHIP-SELECTUNITRegister Mnemonic Register NameRegister Function CHIP-SELECTUNITRegister Mnemonic Register NameRegister Function CHIP-SELECTUNITRegister Mnemonic MPCSCHIP-SELECTUNIT Figure 6-9.MPCS Register Definition6.4.2Programming the Active Ranges CHIP-SELECTUNIT 6.4.2.2LCS Active Range Table 6.3 LCS Active Range6.4.2.3MCS Active Range Table 6-4.MCS Active RangeStarting Address Table 6-6.PCS Active Range 6.4.3Bus Wait State and Ready ControlCHIP-SELECTUNIT 6.4.2.4PCS Active Range BUS READY R2 Control Bit Wait 6.4.4Overlapping Chip-SelectsWait State Value R1:0 State Counter READY Wait State Ready6.4.6Programming Considerations 6.4.5Memory or I/O Bus Cycle DecodingCSU Chip Select Device select 6.6.1Example 1: Typical System ConfigurationExternal Master Chip Select 6.5CHIP-SELECTSAND BUS HOLDFigure 6-13.Typical System CHIP-SELECTUNITExample 6-1.Initializing the Chip-SelectUnit CHIP-SELECTUNITCHIP-SELECTUNIT Place memory variables here CHIP-SELECTUNITRefresh Control Unit Page CHAPTER REFRESH CONTROL UNIT 7.3REFRESH CONTROL UNIT OPERATION 7.1THE ROLE OF THE REFRESH CONTROL UNIT7.2REFRESH CONTROL UNIT CAPABILITIES Refresh Control Unit Operation Set E Bit Figure 7-3.Refresh Address Formation 7.4REFRESH ADDRESSESREFRESH CONTROL UNIT 7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERS 7.5REFRESH BUS CYCLESREFRESH CONTROL UNIT Table 7-1.Identification of Refresh Bus CyclesT3/TW 7.7.1Calculating the Refresh Interval 7.7PROGRAMMING THE REFRESH CONTROL UNIT7.7.2Refresh Control Unit Registers REFRESH CONTROL UNITRegister Mnemonic RFBASERegister Name:Refresh Base Address Register RFTIME Refresh Clock Interval RegisterSets refresh rate Register NameRegister Name Register Mnemonic Register Function 7.7.3Programming ExampleRefresh Control Register RFCON Controls Refresh Unit operationExample 7-1.Initializing the Refresh Control Unit REFRESH CONTROL UNITREFRESH CONTROL UNIT 7.8REFRESH OPERATION AND BUS HOLDCLKOUT Page Interrupt Control Unit Page 8.1FUNCTIONAL OVERVIEW CHAPTER INTERRUPT CONTROL UNIT8.2.1Generic Functions in Master Mode 8.2MASTER MODEINTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking Table 8-1.Default Interrupt Priorities8.2.1.2Interrupt Priority Interrupt Name8.2.1.3Interrupt Nesting INTERRUPT CONTROL UNIT8.3.1Typical Interrupt Sequence 8.3FUNCTIONAL OPERATION IN MASTER MODE8.3.2Priority Resolution •the Interrupt Control Unit has been initialized 8.3.2.2Interrupts That Share a Single Source 8.3.3Cascading with External 8259AsINTERRUPT CONTROL UNIT INT0 8.3.5Polling 8.3.4Interrupt Acknowledge SequenceINTERRUPT CONTROL UNIT Table 8-2.Fixed Interrupt Types8.3.7Additional Latency and Response Time 8.3.6Edge and Level Triggering8.4PROGRAMMING THE INTERRUPT CONTROL UNIT INTERRUPT CONTROL UNIT 8.4.1Interrupt Control RegistersRegister Mnemonic: TCUCON, DMA0CON, DMA1CON Register Mnemonic I2CON, I3CONINTERRUPT CONTROL UNIT I0CON, I1CONRegister Mnemonic Interrupt Request Register 8.4.2Interrupt Request RegisterREQST Stores pending interrupt requestsIMASK Interrupt Mask RegisterMasks individual interrupt sources 8.4.4Priority Mask RegisterRegister Name 8.4.5In-ServiceRegisterPriority Mask Register Register MnemonicFigure 8-10. In-ServiceRegister 8.4.6Poll and Poll Status RegistersRegister Name Register MnemonicPoll Register POLL Register Name Register Mnemonic Register FunctionINTERRUPT CONTROL UNIT Figure 8-11.Poll RegisterRead to check for pending interrupts when polling 8.4.7End-of-InterruptEOI RegisterRegister Name Register Mnemonic Register Function Poll Status Register POLLSTSUsed to issue an EOI command 8.4.8Interrupt Status RegisterRegister Name Register Mnemonic Register Function End-of-InterruptRegister EOIInterrupt Status Register INTSTS 8.5SLAVE MODERegister Name Register Mnemonic Register Function INT0 INTA 80186 Modular Core Select IRQ Figure 8-15.Interrupt Control Unit in Slave Mode8259A 82C59A8.5.1Slave Mode Programming 8.5.1.1Interrupt Vector Register Table 8-5.Slave Mode Fixed Interrupt Type BitsINTERRUPT CONTROL UNIT Register Mnemonic INTVECINTERRUPT CONTROL UNIT 8.5.1.2End-Of-InterruptRegisterUsed to issue the EOI command End-of-InterruptRegister in Slave ModeRegister Name Register Mnemonic8.5.2Interrupt Vectoring in Slave Mode Interrupt presented to Interrupt Control Unit INTERRUPT CONTROL UNIT Page Timer/Counter Unit Page 9.1FUNCTIONAL OVERVIEW CHAPTER TIMER/COUNTER UNITT0 In T1IN T0OUT T1OUT TIMER/COUNTER UNITT0IN Figure 9-3.Timers 0 and 1 Flow Chart TIMER/COUNTER UNITFigure 9-3.Timers 0 and 1 Flow Chart Continued TIMER/COUNTER UNITDual Maximum Count Mode 9.2PROGRAMMING THE TIMER/COUNTER UNITSingle Maximum Count Mode Maxcount ADefines Timer 0 and 1 operation Timer 0 and 1 Control Registers T0CON, T1CONTIMER/COUNTER UNIT Figure 9-5.Timer 0 and Timer 1 Control RegistersRegister Name Register Mnemonic Register Function TIMER/COUNTER UNITDefines Timer 2 operation Timer 2 Control Register T2CONTIMER/COUNTER UNIT Figure 9-6.Timer 2 Control RegisterContains the current timer count Timer Count RegisterT0CNT, T1CNT, T2CNT TIMER/COUNTER UNIT9.2.1Initialization Sequence 9.2.3Counting Modes 9.2.2Clock SourcesTIMER/COUNTER UNIT Table 9-1.Timer 0 and 1 Clock Sources9.2.3.1Retriggering TIMER/COUNTER UNITTable 9-2.Timer Retriggering 9.2.4Pulsed and Variable Duty Cycle OutputTIMER/COUNTER UNIT Timer Serviced 1 9.2.5Enabling/Disabling CountersInternal Count Value Maxcount -9.3.1Input Setup and Hold Timings 9.2.6Timer Interrupts9.2.7Programming Considerations 9.3TIMING9.3.3Real-TimeClock 9.3.2Synchronization and Maximum Frequency9.3.4Square-WaveGenerator 9.3.5Digital One-ShotExample 9-1.Configuring a Real-TimeClock TIMER/COUNTER UNITTIMER/COUNTER UNIT enable interrupts TIMER/COUNTER UNITExample 9-2.Configuring a Square-WaveGenerator TIMER/COUNTER UNITExample 9-3.Configuring a Digital One-Shot TIMER/COUNTER UNITTIMER/COUNTER UNIT Page Direct Memory Access Unit Page 10.1.1 The DMA Transfer CHAPTER DIRECT MEMORY ACCESS UNIT10.1 FUNCTIONAL OVERVIEW Fetch 10.1.3 DMA Requests 10.1.2 Source and Destination Pointers10.1.4 External Requests Fetch Cycle 10.1.5 Internal Requests 10.1.5.1Timer 2-InitiatedTransfersDIRECT MEMORY ACCESS UNIT 10.1.6 DMA Transfer Counts10.1.7.1Termination at Terminal Count 10.1.7.2Software Termination10.1.10 The Two-ChannelDMA Unit 10.1.8 DMA Unit Interrupts10.1.9 DMA Cycles and the BIU Module 10.2.1 DMA Channel Parameters 10.2 PROGRAMMING THE DMA UNITRegister Mnemonic DxSRCHRegister Name:DMA Source Address Pointer High Register Mnemonic DxSRCLRegister Name:DMA Source Address Pointer Low Register Mnemonic DIRECT MEMORY ACCESS UNITDxDSTH Register FunctionRegister Mnemonic DxDSTLRegister Name:DMA Destination Address Pointer Low DxCON DMA Control RegisterControls DMA channel parameters DIRECT MEMORY ACCESS UNITRegister Name DIRECT MEMORY ACCESS UNITDMA Control Register Register MnemonicDMA Control Register Register NameRegister Mnemonic DxCON10.2.1.4Arming the DMA Channel DIRECT MEMORY ACCESS UNIT10.2.1.5Selecting Channel Synchronization 10.2.1.6Programming the Transfer Count OptionsDxTC DMA Transfer CountContains the DMA channel’s transfer count Register Name10.2.3 Initializing the DMA Unit 10.2.2 Suspension of DMA Transfers10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT 10.3.1 DRQ Pin Timing Requirements10.3.3 DMA Transfer Rates 10.3.2 DMA Latency10.4 DMA UNIT EXAMPLES 10.3.4 Generating a DMA AcknowledgeExample 10-1.Initializing the DMA Unit DIRECT MEMORY ACCESS UNITExample 10-1.Initializing the DMA Unit Continued DIRECT MEMORY ACCESS UNITSECTORS DIRECT MEMORY ACCESS UNITExample 10-1.Initializing the DMA Unit Continued Example 10-2.Timed DMA Transfers DIRECT MEMORY ACCESS UNITExample 10-2.Timed DMA Transfers Continued DIRECT MEMORY ACCESS UNITPage Math Coprocessing Page 11.2 AVAILABILITY OF MATH COPROCESSING CHAPTER MATH COPROCESSING11.1 OVERVIEW OF MATH COPROCESSING 11.3.1 80C187 Instruction Set 11.3 THE 80C187 MATH COPROCESSOR•the 80C187 uses register or memory operands Table 11-2.80C187 Arithmetic Instructions MATH COPROCESSINGAddition DivisionTable 11-3.80C187 Comparison Instructions MATH COPROCESSING 11.3.1.3Comparison Instructions11.3.1.4Transcendental Instructions Table 11-4.80C187 Transcendental InstructionsTable 11-5.80C187 Constant Instructions MATH COPROCESSING 11.3.1.5Constant Instructions11.3.1.6Processor Control Instructions Table 11-6.80C187 Processor Control Instructions11.4 MICROPROCESSOR AND COPROCESSOR OPERATION 11.3.2 80C187 Data TypesFigure 11-1. 80C187-SupportedData Types MATH COPROCESSING80C187 MATH COPROCESSINGModular Core11.4.1 Clocking the 80C187 11.4.2 Processor Bus Cycles Accessing the 80C187MATH COPROCESSING Table 11-7.80C187 I/O Port Assignments11.4.3 System Design Tips 80C187 MATH COPROCESSINGModular Core11.5 EXAMPLE MATH COPROCESSOR ROUTINES 11.4.4 Exception Trapping80C186 MATH COPROCESSINGModular Core 80C187MATH COPROCESSING MATH COPROCESSING ONCE Mode Page 12.1 ENTERING/LEAVING ONCE MODE CHAPTER ONCE MODEFigure 12-1.Entering/Leaving ONCE Mode ONCE MODEbidirectional weakly held pins except OSCOUT NOTES: 1. Entering ONCE Mode 2.Latching ONCE Mode80C186 Instruction Set Additions and Extensions Page PUSHA/POPA A.1 80C186 INSTRUCTION SET ADDITIONSA.1.1 Data Transfer Instructions INS source_string, port A.1.2 String InstructionsOUTS port, destination_string A.1.3 High-LevelInstructions1.Main has variables at fixed locations Figure A-3.Stack Frame for Main at Level Figure A-2.Variable Access in Nested Procedures80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Figure A-4.Stack Frame for Procedure A at Level BPA = BP Value for Procedure A80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BP SPBP SP 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSOld BP BPM BPM BPM BPA BPA BPM BPA BPB Display B Dynamic Storage B80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS LEAVEA.2 80C186 INSTRUCTION SET ENHANCEMENTS BOUND register, addressA.2.1 Data Transfer Instructions PUSH dataIMUL destination, source, data A.2.2 Arithmetic InstructionsA.2.3 Bit Manipulation Instructions SAL destination, countROR destination, count ROL destination, countRCL destination, count RCR destination, countInput Synchronization Page APPENDIX B INPUT SYNCHRONIZATION B.1 WHY SYNCHRONIZERS ARE REQUIREDB.2 ASYNCHRONOUS PINS Instruction Set Descriptions Page Table C-1.Instruction Format Variables APPENDIX C INSTRUCTION SET DESCRIPTIONSTable C-2.Instruction Operands INSTRUCTION SET DESCRIPTIONSOperand DescriptionTable C-3.Flag Bit Functions INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set INSTRUCTION SET DESCRIPTIONSADC dest, src INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSName DescriptionCALL procedure-name Call ProcedureINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSINSTRUCTION SET DESCRIPTIONS Clear Interrupt-enableFlagTable C-4.Instruction Set Continued NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-10 NameC-11 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-12 NameWhen Source Operand is a Word When Source Operand is a ByteINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Procedure EntryTable C-4.Instruction Set Continued C-14Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-15 NameWhen Source Operand is a Word When Source Operand is a ByteINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-17 IN accum, portTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-18 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-19 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-20 JA disp8Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSJAE disp8 JNB disp8Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSJE disp8 JZ disp8Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSJL disp8 JGE disp8Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSJNE disp8 JNZ disp8Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSJO disp8 JP disp8Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-26 LDS dest, srcINSTRUCTION SET DESCRIPTIONS Load Pointer Using ESTable C-4.Instruction Set Continued C-27Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-28 LODS src-stringTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-29 MOV dest, srcTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-30 MOVS dest-string, src-stringC-31 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-32 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-33 NameC-34 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-35 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-36 NameC-37 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued Table C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-38 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-39 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSSHL dest, count SAL dest, countTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-41 NameWhen Source Operand is a Word When Source Operand is a ByteINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-43 SHR dest, srcTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-44 STOS dest-stringTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-45 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-46 NameTable C-4.Instruction Set Continued INSTRUCTION SET DESCRIPTIONSC-47 NamePage Instruction Set Opcodes and Clock Cycles Page Table D-1.Operand Variables APPENDIX D INSTRUCTION SET OPCODESAND CLOCK CYCLES Table D-2.Instruction Set Summary INSTRUCTION SET OPCODES AND CLOCK CYCLESFunction FormatTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESDATA TRANSFER INSTRUCTIONS Continued ARITHMETIC INSTRUCTIONSARITHMETIC INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued Table D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESARITHMETIC INSTRUCTIONS Continued BIT MANIPULATION INSTRUCTIONSTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESBIT MANIPULATION INSTRUCTIONS Continued Shifts/RotatesTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESPROGRAM TRANSFER INSTRUCTIONS Continued Iteration ControlTable D-2.Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-3.Machine Instruction Decoding Guide ByteByte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Table D-4.Mnemonic Encoding Matrix Left Half INSTRUCTION SET OPCODES AND CLOCK CYCLESD-21 INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-4.Mnemonic Encoding Matrix Right Half Abbr INSTRUCTION SET OPCODES AND CLOCK CYCLESDefinition AbbrIndex Page ARDY, See READY Arithmetic INDEXData bus, See Address and data bus INDEXCrystal‚ See Oscillator See also Bus cycles INDEXSee also Refresh Control Unit Index-3interrupt INDEXIndex-4 Index-5 INDEXIndex-6 INDEXIndex-7 Timers‚ See Timer Counter Unit TCUINDEX Index-8 INDEX