Intel 80C186XL, 80C188XL 7.4REFRESH ADDRESSES, Refresh Control Unit, 3.Refresh Address Formation

REFRESH CONTROL UNIT

The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another request before the BIU handles the present request, the BIU loses the present request. However, the address associated with the request is not lost. The refresh address changes only after the BIU runs a refresh bus cycle. If a DRAM refresh cycle is excessively delayed, there is still a chance that the processor will successfully refresh the corresponding row of cells in the DRAM, retaining the data.

7.4REFRESH ADDRESSES

Figure 7-3 shows the physical address generated during a refresh bus cycle. This figure applies to both the 8-bit and 16-bit data bus microprocessor versions. Refresh address bits RA19:13 come from the Refresh Base Address Register. (See “Refresh Base Address Register” on page 7-8.)

	From Refresh Base
	Address Register							Fixed				From Refresh Address Counter Fixed
RA	RA	RA	RA	RA	RA	RA	0		0	0		RA	RA	RA	RA	RA	RA	RA	RA	RA	1
19	18	17	16	15	14	13					9		8	7	6	5	4	3	2	1
19																				0
								20-Bit Refresh Address

A1502-0A

Figure 7-3. Refresh Address Formation

Refresh address bits RA12:10 are always zero. A linear-feedback shift counter generates address bits RA9:1 and RA0 is always one. The counter does not count linearly from 0 through 1FFH. However, the counting algorithm cycles uniquely through all possible 9-bit values. It matters only that each row of DRAM memory cells is refreshed at a specific interval. The order of the rows is unimportant.

Address bit A0 is fixed at one during all refresh operations. In applications based on a 16-bit data bus processor, A0 typically selects memory devices placed on the low (even) half of the bus. Ap- plications based on an 8-bit data bus processor typically use A0 as a true address bit. The DRAM controller must not route A0 to row address pins on the DRAMs.

7-4