Intel 80C186XL, 80C188XL user manual 3.8BUS CYCLE PRIORITIES

Models: 80C186XL 80C188XL

1 405
Download 405 pages 42.62 Kb
Page 125
Image 125
3.8BUS CYCLE PRIORITIES

BUS INTERFACE UNIT

CLKOUT

1

2

3

4

5

HOLD

HLDA

AD15:0

DEN

RD, WR, BHE,

DT/R, S2:0,

A19:16, LOCK

NOTES:

1.THVCL : HOLD recognition setup to clock low

2.: HOLD internally synchronized

3.TCLHAV : Clock low to HLDA low

4.TCHCV : Clock high to signal active (high or low)

5.TCLAV : Clock low to signal active (high or low)

A1063-0A

Figure 3-37. Exiting HOLD

3.8BUS CYCLE PRIORITIES

The BIU arbitrates requests for bus cycles from the Execution Unit, the integrated peripherals (e.g., Interrupt Control Unit) and external bus masters (i.e., bus hold requests). The list below summarizes the priorities for all bus cycle requests (from highest to lowest).

1.Instruction execution read/write following a non-pipelined effective address calculation.

2.Refresh bus cycles.

3.Bus hold request.

4.Single step interrupt vectoring sequence.

5.Non-Maskable interrupt vectoring sequence.

3-44

Page 125
Image 125
Intel 80C186XL, 80C188XL user manual 3.8BUS CYCLE PRIORITIES