CLOCK GENERATION AND POWER MANAGEMENT

X1

Vcc

Vcc and X1 stable to output valid 28 X1 periods (max)

CLKOUT

UCS, LCS

MCS3:0, NCS

TMR OUT0

TMR OUT1

PCS6:0

HLDA, ALE

A19:16

AD15:0, S2:0

RD, WR, DEN

DT/R, LOCK

RES

RESET

Vcc and X1 stable to RES high, approximately 32 X1 periods.

RES high to first bus activity,

7 CLKOUT periods.

NOTE: CLKOUT synchronization occurs 1 1/2 X1 periods after RES is sampled low.

A1508-0B

Figure 5-6. Cold Reset Waveform

5-8

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Image 147
Intel 80C186XL, 80C188XL user manual Cold Reset Waveform