Or TW Or TI, Clkout RD/ WR | Intel 80C186XL, 80C188XL manual

BUS INTERFACE UNIT

		T3	T4
	T2	or TW	or TI
	CLKOUT
	1	2	4
	RD/ WR		6
			7
	AD15:0	Valid Write Data	5
	Write	Valid Write Data	5
	Write
		3
	AD15:0		Valid
	Read	Read Data

S2:0

NOTES:

1.TCLRL/CLWL, TCLOV : Clock low to valid RD/WR active, write data valid.

2.TCLSH : Clock low to status inactive.

3.TDVCL : Data input valid to clock low.

4.TCLRH/CLWH : Clock valid to RD/WR inactive.

5.TCLDX : Data input HOLD from clock low.

6.TWHDX : Output data HOLD from WR high.

7.TRHAV : Bus no longer floating from RD high.

Figure 3-12. Data Phase Signal Relationships

3-14

Image 95

Intel 80C186XL, 80C188XL user manual Or TW Or TI, Clkout RD/ WR, AD150 Valid Write Data Read Read Data S20

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual Intel Corporation Contents Contents LCS Setting the PCB Base LocationPower Management Clock Generation Chapter Refresh Control Unit Functional Overview Functional Overview Programming the TIMER/COUNTER UnitProgramming the Interrupt Control Unit Chapter Math Coprocessing Chapter Once Mode Figures UCS Reset Configuration Interrupt Control Register for Noncascadable External Pins 10-9 Tables Flag Bit Functions Example Examples Introduction Page Chapter Introduction Comparison of 80C186 Modular Core Family Products HOW to USE this ManualFeature 80C186XL 80C186EA 80C186EB 80C186EC Document/Software Title Order No Related DocumentsRelated Documents and Software Electronic Support Systems FaxBack Service Bulletin Board System BBS Technical Support CompuServe ForumsWorld Wide Web Training Classes Product LiteraturePage Overview 80C186 Family Architecture Page Architectural Overview Chapter Overview of the 80C186 Family Architecture Execution Unit Simplified Functional Block Diagram of the 80C186 Family CPU Physical Address Generation Bus Interface Unit General Registers General Registers Operations Segment RegistersImplicit Use of General Registers Segment Registers Instruction Pointer Flags Memory Segmentation Register Function Register NameRegister Mnemonic PSW Flags Segment Locations in Physical Memory Logical Addresses Fffffh Data DS Code CS Stack SS Extra ES 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH Logical Address Sources Type of Memory Reference Default Alternate OffsetDynamically Relocatable Code Segment Data Extra Before After Relocation Code SegmentSegment Code Data Reserved Memory and I/O Space Stack Implementation 10. Stack Operation Instruction Set Software Overview Input/Output Data Transfer InstructionsGeneral-Purpose 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Lahf S Z U a U P U CSahf 7 6 5 4 3 2 1 Pushf Popf U U O D I T S Z U a U P U C Division AdditionSubtraction Multiplication Shifts Arithmetic Interpretation of 8-Bit NumbersBit Manipulation Instructions Hex Bit Pattern Unsigned Signed Unpacked Packed Binary String Instructions CX AL/AX String Instruction Register and Flag UseProgram Transfer Instructions Overview of the 80C186 Family Architecture Interrupts Conditional TransfersUnconditional Transfers Iteration Control Mnemonic Condition Tested Jump if… 10. Interpretation of Conditional Transfers Register and Immediate Operand Addressing Modes Addressing ModesProcessor Control Instructions 11. Processor Control Instructions Memory Addressing Modes BIU 0000 Physical Addr 13. Direct Addressing Opcode Mod R/M Displacement 15. Based Addressing 14. Register Indirect Addressing Register Dept Div Employee Age Displacement High Address Rate AgeRate Base Vac Base Register 17. Indexed Addressing 18. Accessing an Array with Indexed Addressing 19. Based Index Addressing 20. Accessing a Stacked Array with Based Index Addressing Opcode Source EA Destination EA BCD Data Types Used in the 80C186 Modular Core Family12. Supported Data Types Type Description 23 C186 Modular Core Family Supported Data Types Interrupt/Exception Processing Interrupts and Exception Handling 3FC 3FE Overview of the 80C186 Family Architecture Trap Flag Interrupt Enable BitStack PSW Exceptions Maskable Interrupts Invalid Opcode Type Interrupt Latency Software Interrupts Interrupt and Exception Priority Interrupt Response TimeClocks Total Iret Execute Divide Service RoutineNMI 29. Simultaneous NMI and Single Step Interrupts Trap Flag = ??? 30. Simultaneous NMI, Single Step and Maskable Interrupt Interrupt Enable Bit IE = Trap Flag TF =Page Bus Interface Unit Page 1 16-Bit Data Bus Multiplexed Address and Data BUSAddress and Data BUS Concepts A190 D70 A191 D158 Physical Implementation Address Space forMByte KBytes Fffff Ffffe Ffffd Ffffc D70 A0 Low A191 D158 BHE High Even Byte TransferA191 D158 BHE High Odd Byte Transfer Bit Data Bus Even Word Transfers A191 D158 BHE Low D70 A0 Low D70 A0 High A191 D158 BHE Low First Bus CycleA191 D158 BHE Low Second Bus Cycle Bit Data Bus Word Transfers Memory and I/O Interfaces BUS Cycle Operation 1 16-Bit Bus Memory and I/O Requirements2 8-Bit Bus Memory and I/O Requirements S20 Valid Status AD150 Address Data PhaseLow Phase High Phase Clkout ALE RES# Bus ReadyRequest Pending Hold Deasserted Clkout Address Status Phase Or TW Or TI Data PhaseAddress/Status Phase Or TI S20 A1916 ALE STB STB Wait States Data Phase AD150 Valid Write Data Read Read Data S20 Or TW Or TIClkout RD/ WR BUS Ready ReadyArdy Clkout Srdy CS1 CS2 CS3 CS4 ALE Clkout Clock 16. Generating a Normally Ready Bus Signal Idle States Clkout Ardy Srdy 18. Normally Ready System Timings Read Cycle Critical Timing Parameters BUS CyclesRead Bus Cycles Read Bus Cycle Types DT/R DEN A158Rfsh A150 LA151 AD158 UCSAD70 O0-7 27C256 Status Bits Bus Cycle Type A158 A150Write Bus Cycle Types LCS LA151LA0 BHE A014 O18 CS1 AD70 AD158 Write Cycle Critical Timing Parameters Interrupt Acknowledge Bus Cycle BHE RD, WR INTA0 INTA1Lock DT/R DEN System Design Considerations Processor 82C59AINTA0 Inta INT0 IR0 IR7 PCS0 LA1 Halt Bus Cycle BHE Pins Pin State011 AD150 AD70 A158 A1916 Rfsh = Control Temporarily Exiting the Halt Bus StateClkout Hold Hlda AD150 AD70 A158 A1916 BHE Rfsh S20 AD150 AD70 A158 A1916 RFSH=1 T4 T1 T2 T3T3 TI TI TI TI AD70 A158 System Design Alternatives NMI/INTx Clkout RD,WR DT/R DEN Buffering the Data Bus CPU Local Bus Buffered Bus DeviceDT/ R Synchronizing Software and Hardware Events MCS0Buffer Buffered Data Bus AD70 Buffer Local Data Bus Using a Locked Bus No queue operation occurred Using the Queue Status SignalsQueue Status Signal Decoding Queue Status Entering Bus Hold MULTI-MASTER BUS System Designs Lock Signal Hold ConditionFloat RD, W R Float BHE , S20 Refresh Operation During a Bus Hold DT/R Lock Clkout Hold Hlda DEN RD, WRBHE, S20 Exiting Hold Hlda Reset Hold PRE CLRLatched Hlda BUS Cycle Priorities DEN RD, WR, BHEDT/R, S20 A1916, Lock BUS Interface Unit Page Peripheral Control Block Page PCB Relocation Register Peripheral Control Registers Relreg Bit Bit Name Reset Function Mnemonic StateRegister Name PCB Relocation Register Register Mnemonic Peripheral Control Block Bus Cycles Accessing the Peripheral Control BlockReady Signals and Wait States Reserved Locations Word reads Bus Operation Writing the PCB Relocation Register Setting the PCB Base LocationAccessing the Peripheral Control Registers Accessing Reserved Locations Considerations for the 80C187 Math Coprocessor Interface Page Clock Generation Power Management Page Crystal Oscillator Clock GenerationRES Oscillator Operation = Inverter Output Z 90˚ 180˚ Crystal Connections to Microprocessor Values µH Third-Overtone Crystal Inductor L1 Selecting Crystals Output from the Clock Generator Using an External OscillatorReset and Clock Synchronization 1µf typical Typical Ct = V 1 e Cold Reset Waveform Clkout PCS60,NCS RES Resync Clkout ResetPower Management Entering Power-Save Mode Power-Save Mode Pwrsav Power Save RegisterEnables and sets clock division factor Register Name Register Mnemonic Register Function Example Power-Save Initialization Code 10. Power-Save Clock Transition Leaving Power-Save Mode Syntax Chip-Select Unit Page Common Methods for Generating CHIP-SELECTS CHIP-SELECT Unit Features and Benefits 74AC138 Chip-Selects Using Addresses Directly Simple DecoderCHIP-SELECT Unit Functional Overview 27C256 PCS1 MCS3MCS2 MCS1 MCS30, LCS A1916 UCS, PC S60 1MB 1AddressSrdy Ardy UCS Data Active For Top 1 KByte Memory Map Control Register Alternate Register ProgrammingInitialization Sequence Chip-Select Unit Registers Controls the operation Chip-select UCS Control RegisterUmcs Lmcs LCS Control Register MCS MCS Control RegisterMmcs Controls the operation Chip-selects PCS PCS Control RegisterPacs X S Register NameMCS and PCS Alternate Control RegisterMpcs Umcs Field Block Size Starting Address U1710 Programming the Active RangesUCS Active Range UCS Block Size and Starting Address Lmcs Field Block Size Ending Address U1710 LCS Active RangeLCS Active Range MCS Active Range Block Size Mmcs Start Address Kbytes Restrictions MCS Block Size and Start Address Restrictions PCS Active Range Bus Wait State and Ready Control Overlapping Chip-Selects R2 Control Bit Wait Wait State Value R10 State CounterWait State Ready Programming Considerations Memory or I/O Bus Cycle Decoding Examples Example 1 Typical System ConfigurationCHIP-SELECTS and BUS Hold 13. Typical System MOD186XREF Name CSUEXAMPLE1 Example 6-1. Initializing the Chip-Select Unit Drambase EQU Place memory variables here Refresh Control Unit Page CLR REQ CPU Refresh Control Unit Operation Role of the Refresh Control UnitRefresh Control Unit Capabilities Refresh Control Unit Operation Flow Chart Refresh Address Formation Refresh Addresses Data Bus Width Refresh BUS CyclesGuidelines for Designing Dram Controllers Identification of Refresh Bus Cycles RAS CAS T3/TW ClkoutMuxed Row Column Address S20 Refresh Control Unit Registers Programming the Refresh Control UnitCalculating the Refresh Interval Refresh Base Address Register Register NameRefresh Base Address RegisterRfbase Register FunctionDetermines upper 7 bits of refresh address Register Function Sets refresh rate Rftime Programming Example Refresh Control RegisterRfcon Controls Refresh Unit operation Example 7-1. Initializing the Refresh Control Unit Refresh Operation and BUS Hold RD, WR BHE, S2 DT / R A1916 Clkout Hold Hlda DENPage Interrupt Control Unit Page Functional Overview Chapter Interrupt Control Unit DMA Master ModeTimer 0 Timer 1 Timer Generic Functions in Master Mode Interrupt Name Relative Priority Default Interrupt PrioritiesInterrupt Masking Interrupt Priority Interrupt Nesting Typical Interrupt Sequence Functional Operation in Master ModePriority Resolution Priority Resolution Example Interrupts That Share a Single Source Cascading with External 8259As Inta INTA1 INT INT0Inta INTA0 INT INT1 Interrupt Name Interrupt Type Interrupt Acknowledge SequencePolling Fixed Interrupt Types Additional Latency and Response Time Edge and Level Triggering Programming the Interrupt Control Unit Inta IdleInta Idle Read IP Read CS Idle Push Flags Push CS Push IP 2AH Interrupt Control Registers2CH MSK Interrupt Control Register for Internal Sources LVL Register NameInterrupt Control Register non-cascadable pinsI2CON, I3CON CAS Register NameInterrupt Control Register cascadable pinsI0CON, I1CON Sfnm Register Function Stores pending interrupt requests Interrupt Request RegisterRegister Name Interrupt Request Register Register Mnemonic Reqst Priority Mask Register Register Name Interrupt Mask Register Register MnemonicImask Register Function Masks individual interrupt sources Masks lower-priority interrupt sources In-Service RegisterPriority Mask Register Primsk Poll and Poll Status Registers In-Service RegisterInserv Indicates which interrupt handlers are in process Ireq Poll RegisterPoll End-of-Interrupt EOI Register Read to check for pending interrupts when pollingPoll Status Register Pollsts Interrupt Status Register Used to issue an EOI commandEnd-of-Interrupt Register EOI Dhlt Slave ModeInterrupt Status Register Intsts IRQ INT VCC INT0 Inta 16. Interrupt Sources in Slave Mode Slave Mode Programming Interrupt Control Unit Register Comparison Slave Mode Fixed Interrupt Type BitsMaster Mode Slave Mode PCB Offset Register Name Interrupt Vector Register Intvec Register NameInterrupt Vector Register Slave Mode only Used to issue the EOI command End-of-Interrupt Register in Slave Mode CAS20 Slave Cascade Address From 8259A Interrupt Vectoring in Slave ModeT1 T2 T3 T4 Inta INTA0 Select Lock Inta Idle Read IP Read CS Push Flags Push CS Push IP Initializing the Interrupt Control Unit for Master Mode Priorities are used Page Timer/Counter Unit Page Chapter TIMER/COUNTER Unit Interrupt Latch Clock Timer Element Registers Output Latch T0IN T1IN T0OUT T1OUT Counter Element Multiplexing and Timer Input Synchronization Timers 0 and 1 Flow Chart From Timer/Counter Unit Output Modes Programming the TIMER/COUNTER Unit T0CON, T1CON Timer 0 and 1 Control RegistersDefines Timer 0 and 1 operation Cont RTGEXT ALT Maximum count. The MC bit must be cleared Timer 2 Control RegisterDefines Timer 2 operation T2CON C C Register Name Timer Count Register Register MnemonicRegister Function Contains the current timer count T0CNT, T1CNT, T2CNT Timer Maxcount Compare Registers Clock Source Timer 0 and 1 Clock SourcesClock Sources Counting Modes Retriggering Pulsed and Variable Duty Cycle Output Timer RetriggeringTimer Operation Enabling/Disabling Counters Timer Serviced Internal Count Value Maxcount TxOUT Pin Timing Timer InterruptsInput Setup and Hold Timings Square-Wave Generator Timer/Counter Unit Application ExamplesSynchronization and Maximum Frequency Real-Time Clock Intsts Example 9-1. Configuring a Real-Time Clock Out Dx, al Timer2interruptroutine proc far T1CON Example 9-2. Configuring a Square-Wave Generator Example 9-3. Configuring a Digital One-Shot Cmpb Page Direct Memory Access Unit Page DMA Transfer Chapter Direct Memory Access Unit Typical DMA Transfer Fetch Deposit Byte and Word Transfers Source and Destination PointersDMA Requests DMA Transfer Directions DRQ External RequestsT1 or T2 or T3 or TW or T4 or Cycle Source Synchronization DRQ Case Case Timer 2-Initiated TransfersFetch Cycle Deposit Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TI Clkout DRQ Termination and Suspension of DMA Transfers DMA Transfer Counts DMA Channel Arbitration DMA Unit InterruptsDMA Cycles and the BIU Two-Channel DMA Unit Two-Channel DMA Module Module DMA Channel Parameters SRCProgramming the DMA Unit DMA Xxxxh Register NameDMA Source Address Pointer HighRegister Mnemonic DxSRCH S S a a Register NameDMA Source Address Pointer LowRegister Mnemonic DxSRCL Contains the upper 4 bits of the DMA Destination pointer Register NameDMA Destination Address Pointer HighDxDSTH Register Mnemonic DxDSTL Register NameDMA Destination Address Pointer Low Dinc D I E N C C C N TDmem Ddec Idrq Synchronization Type Word CHGStrt Programming the Transfer Count Options Arming the DMA ChannelSelecting Channel Synchronization Generating Interrupts on Terminal Count Setting the Relative Priority of a Channel DRQ Pin Timing Requirements Suspension of DMA TransfersInitializing the DMA Unit Hardware Considerations and the DMA Unit DMA Transfer Rates DMA Latency DMA Unit Examples Generating a DMA Acknowledge MOV DS, AX Assume Dsdataseg Example 10-1. Initializing the DMA Unit 10-24 10-25 Example 10-2. Timed DMA Transfers 10-27 Page Math Coprocessing Page Availability of Math Coprocessing Overview of Math Coprocessing 11.3.1 80C187 Instruction Set 80C187 Math Coprocessor Packed Decimal Transfers C187 Data Transfer InstructionsReal Transfers Integer Transfers Other Operations C187 Arithmetic Instructions C187 Transcendental Instructions Comparison InstructionsC187 Comparison Instructions Transcendental Instructions Fldz FLD1 Fldpi FLDL2T FLDL2E FLDLG2 FLDLN2 Constant InstructionsC187 Constant Instructions C187 Processor Control Instructions Microprocessor and Coprocessor Operation 11.3.2 80C187 Data Types C187-Supported Data Types 80C186 80C187Modular Core Address Read Definition Write Definition Processor Bus Cycles Accessing the 80C187Clocking the 80C187 C187 I/O Port Assignments System Design Tips C187 Configuration with a Partially Buffered Bus Example Math Coprocessor Routines Exception Trapping C187 Exception Trapping via Processor Interrupt Pin 80C186 Modular Core Name Example80C187init Results Example 11-2. Floating Point Math Routine Using Fsincos Once Mode Page ENTERING/LEAVING Once Mode Chapter Once Mode Oscout RES UCS LCS 80C186 Instruction Set Additions Extensions Page Data Transfer Instructions 80C186 Instruction SET Additions High-Level Instructions String Instructions Figure A-1. Formal Definition of Enter Figure A-2. Variable Access in Nested Procedures Figure A-4. Stack Frame for Procedure a at Level BPM BPA BPB Leave 80C186 Instruction SET Enhancements Bound register, address Shift Instructions Arithmetic InstructionsBit Manipulation Instructions Rotate Instructions ROL destination, count Input Synchronization Page Figure B-1. Input Synchronization Circuit WHY Synchronizers are Required Asynchronous Pins Instruction Set Descriptions Page Variable Description Table C-1. Instruction Format Variables Operand Description Table C-2. Instruction Operands Table C-3. Flag Bit Functions Table C-4. Instruction Set Add with Carry Ascii Adjust for SubtractionAAS ADC Dest, src ADDADD dest, src Logical Detect Value Out of Range Call ProcedureCall procedure-name Bound Clear Direction flag Convert Byte to WordClear Carry flag Complement Carry Flag Clear Interrupt-enable Flag Compare String CMPCompare CMP dest, src Convert Word to Doubleword Decimal Adjust for AdditionDecimal Adjust for Subtraction Decrement DEC When Source Operand is a Word Divide When Source Operand is a Byte Escape Procedure EntryEnter locals, levels Halt Integer Divide When Source Operand is a Byte Accum, port Integer Multiply When Source Operand is a ByteInput Byte or Word When Source Operand is a Byte Imul INS dest-string, port INCIncrement String INT interrupt-type Interrupt Jump on Not Below or Equal Interrupt on OverflowInterrupt Return Jump on Above Jump on Not Above or Equal Jump on Above or EqualJump on Not Below Jump on Below Jump on Not Less Than or Equal Jump if CX ZeroJump on Equal Jump on Zero Jump on Greater Than Jump on Not Greater Than Name Description Operation Flags Affected Jump on Less ThanJump on Not Greater Than or Equal Jump on Less Than or Equal Jump on Not Sign Jump on Not EqualJump on Not Zero Jump on Not Overflow Instruction Format Name Description Operation Flags Affected Jump on OverflowJump on Parity Jump on Parity Equal LEA dest, src Load Pointer Using DSLDS dest, src Load Effective Address Lock the Bus Load Pointer Using ESLES dest, src Loop While Equal Load String Byte or Word When Source Operand is a ByteLods src-string Loop MOV dest, src Loop While Not EqualLoop While Not Zero Move Byte or Word MUL Multiply When Source Operand is a ByteMove String Movs dest-string, src-string NEG Negate When Source Operand is a ByteLogical Not When Source Operand is a Byte OUT port, accumulator Name Description Operation Flags Affected Logical orOr dest,src Output Pop Out StringOuts port, srcstring Push Pop AllPop Flags Push Flags Push All RCR dest, count Rotate Through Carry LeftRCL dest, count Rotate Through Carry Right Repeat While Not Equal RepeatRepeat While Equal Repeat While Zero Rotate Left RETReturn RET optional-pop-value Store Register AH Into Flags Rotate RightROR dest, count Shift Arithmetic Right Shift Logical LeftShift Arithmetic Left SBB dest, src SBBSubtract With Borrow Scas dest-string Scan String When Source Operand is a Byte Set Direction Flag Shift Logical RightSHR dest, src Set Carry Flag Stos dest-string Set Interrupt-enable FlagStore Byte or Word String When Source Operand is a Byte Test SUBSubtract SUB dest, src Xchg dest, src WaitExchange XOR dest, src TranslateXlat translate-table Exclusive OrPage Instruction Set Opcodes and Clock Cycles Page Reg Bit w=1 Bit w=0 Table D-1. Operand VariablesEA Calculation Mod Effect on EA Calculation Function Format Clocks Table D-2. Instruction Set Summary Arithmetic Instructions Arithmetic Instructions BIT Manipulation Instructions String Manipulation Instructions JB/JNAE = LOOPNZ/LOOPNE = Processor Control Instructions Table D-3. Machine Instruction Decoding Guide Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AX,CX Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AL,DX Instruction SET Opcodes and Clock Cycles Table D-4. Mnemonic Encoding Matrix Left Half Table D-4. Mnemonic Encoding Matrix Right Half Abbr Definition Table D-5. Abbreviations for Mnemonic Encoding Matrix Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8