Intel 80C186XL, 80C188XL user manual Interrupt Request Register, Reqst, Interrupt Mask Register

INTERRUPT CONTROL UNIT

8.4.2Interrupt Request Register

The Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a source requests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt is masked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An external interrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the Interrupt Request bit will be cleared, but the interrupt will not be serviced.

Register Name:	Interrupt Request Register
Register Mnemonic:	REQST
Register Function:	Stores pending interrupt requests

15

I	I	I	I	D	D
N	N	N	N	M	M
T	T	T	T	A	A
3	2	1	0	1	0

0

T

M

R

A1201-A0

Bit	Bit Name	Reset	Function
Mnemonic		State
INT3:0	External	0000 0	A bit is set to indicate a pending interrupt from
	Interrupts		the corresponding external interrupt pin.
DMA1:0	DMA	0	A bit is set to indicate a pending interrupt from
	Interrupt		the corresponding DMA channel.
TMR	Timer	0	This bit is set to indicate a pending interrupt
	Interrupt		from one of the timers.

NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products.

Figure 8-7. Interrupt Request Register

8.4.3Interrupt Mask Register

The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source. This reg- ister allows you to mask (disable) individual interrupts. Set a mask bit to disable interrupts from the corresponding source. The mask bit is the same as the one in the Interrupt Control register. Modifying a bit in either register also modifies that same bit in the other register.

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