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Intel 80C188XL, 80C186XL user manual Processor

Models: 80C186XL 80C188XL

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BUS INTERFACE UNIT

Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate both bus cycles in the interrupt acknowledge sequence.

NOTE

Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space. In this case, wait states cannot be added to interrupt acknowledge bus cycles. However, you can add wait states to interrupt acknowledge cycles if the PCB is located at any other address.

3.5.3.1System Design Considerations

Although ALE is generated for both bus cycles, the BIU does not drive valid address information. Actually, all address bits except A19:16 float during the time ALE becomes active (on both 8- and 16-bit bus devices). Address-decoding circuitry must be disabled for Interrupt Acknowledge bus cycles to prevent erroneous operation.

Processor		82C59A
INTA0	INTA
INT0	INT	IR0
RD	RD	IR7
WR	WR
PCS0	CS
LA1	A0	D7:0
		D7:0
AD7:0
		A1065-0A
Figure 3-24. Typical 82C59A Interface

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Intel 80C188XL, 80C186XL user manual Processor

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual 1995Intel Corporation Literature Sales P.O. Box CONTENTS CHAPTERINTRODUCTION CHAPTERCONTENTS CHAPTERBUS INTERFACE UNIT CONTENTS CLOCK GENERATION AND POWER MANAGEMENTCHAPTER PERIPHERAL CONTROL BLOCKCONTENTS CHAPTERREFRESH CONTROL UNIT CHAPTERCONTENTS TIMER/COUNTER UNITDIRECT MEMORY ACCESS UNIT CHAPTERCONTENTS CHAPTERMATH COPROCESSING CONTENTS CHAPTERONCE MODE APPENDIX AFIGURES CONTENTSPage CONTENTS FIGURESPage 3-15CONTENTS FIGURESPage 6-11CONTENTS FIGURESPage 10-3TABLES CONTENTSPage CONTENTS TABLESPage D-20EXAMPLES CONTENTSExample PageIntroduction Page CHAPTER INTRODUCTION 1.1HOW TO USE THIS MANUAL INTRODUCTION1.2RELATED DOCUMENTS INTRODUCTIONTable 1-2.Related Documents and Software 1.3.1FaxBack Service 1.3ELECTRONIC SUPPORT SYSTEMS1.3.2Bulletin Board System BBS 1.3.3CompuServe Forums 1.3.4World Wide Web1.4TECHNICAL SUPPORT 1.5PRODUCT LITERATURE 1.6TRAINING CLASSESPage Overview of the 80C186 Family Architecture Page CHAPTER OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1ARCHITECTURAL OVERVIEW 2.1.1Execution Unit OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.2Bus Interface Unit 2.1.3General Registers OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-3.General Registers 2.1.4Segment Registers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-1.Implicit Use of General Registers 2.1.5Instruction Pointer OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-4.Segment Registers 2.1.6Flags 2.1.7Memory Segmentation Register Name Register MnemonicRegister Function Reset2.1.8Logical Addresses Data DS Code CS Stack SS Extra ES B E H JFFFFFH A B D E G J K 0H C F HPhysical Address Offset 3H Segment Base Logical Addresses Segment BaseOffset 13H 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH2.1.9Dynamically Relocatable Code OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-2.Logical Address Sources Before 2.1.10 Stack Implementation 2.1.11 Reserved Memory and I/O SpaceOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-10.Stack Operation2.2SOFTWARE OVERVIEW 2.2.1Instruction SetOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.1Data Transfer InstructionsTable 2-3.Data Transfer Instructions General-PurposeI = Interrupt Enable Flag T = Trap Flag OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-11.Flag Storage Format 2.2.1.2Arithmetic InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-4.Arithmetic InstructionsAddition SubtractionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.3Bit Manipulation InstructionsTable 2-6.Bit Manipulation Instructions Bit PatternOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.4String InstructionsTable 2-7.String Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.5Program Transfer InstructionsSI DI CX AL/AX DF ZF Scan value Destination for LODS Source for STOSUnconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-9.Program Transfer InstructionsConditional Transfers Unconditional TransfersOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE MnemonicCondition Tested “Jump if…”2.2.2Addressing Modes OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.6Processor Control Instructions Table 2-11.Processor Control InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2.2Memory Addressing ModesEncoded in the Instruction Explicit in the Displacement OpcodeMod R/M OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREDisplacement OpcodeMod R/M BX or BPDisplacement Opcode Displacement OpcodeMod R/M BX or BPHigh Address Opcode SI DI Source EA Destination EAOpcode Data Port Address Direct Port AddressingOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-12.Supported Data TypesType DescriptionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE NMI CPU Maskable Interrupt Request Interrupt AcknowledgeInterrupt Control Unit External Interrupt SourcesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-25.Interrupt Vector Table3.The current CS and IP are pushed onto the stack Stack PSW Divide Error — Type Single Step — TypeOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.1.2Maskable InterruptsNumerics Coprocessor Fault — Type Breakpoint Interrupt — TypeInterrupt on Overflow — Type Array Bounds Check — Type2.3.2Software Interrupts 2.3.3Interrupt Latency2.3.4Interrupt Response Time ClocksTotal 2.3.5Interrupt and Exception PriorityDivide Error Push PSW, CS, IP Fetch Divide Error VectorService Routine IRET Execute Divide Service Routine IRETPush PSW, CS, IP Fetch Divide Error Vector Service Routine IRET Trap Flag = ???NMI Instruction Trap Flag =Interrupt Enable Bit IE = Trap Flag TF = Page Bus Interface Unit Page CHAPTER BUS INTERFACE UNIT 3.1MULTIPLEXED ADDRESS AND DATA BUS3.2ADDRESS AND DATA BUS CONCEPTS 3.2.116-BitData Bus1 MByte 512 KBytes512 KBytes Even Byte Transfer Odd Byte TransferA19 D15 8 BHED7:0 A0 Low BUS INTERFACE UNITFirst Bus Cycle Second Bus Cycle3.2.28-BitData Bus A19:0 D7:03.3MEMORY AND I/O INTERFACES First Bus Cycle3.3.116-BitBus Memory and I/O Requirements 3.3.28-BitBus Memory and I/O Requirements3.4BUS CYCLE OPERATION Phase CLKOUTFalling RisingBus Ready 3.4.1Address/Status Phase or TI Signals From CPU 3.4.2Data Phase 3.4.3Wait Statesor TW T1 T2 T3 TW TW T4 CLKOUT CS1 CS2 CS3 CS4 ALE CLKOUT Wait State Module Input InputClear Clock READYWait State Module CS1 Enable CS2 LoadREADY CLKOUT3.4.4Idle States CLKOUTARDY SRDY •The instruction prefetch queue is full 3.5BUS CYCLES 3.5.1Read Bus CyclesBUS INTERFACE UNIT Table 3-2. Read Bus Cycle TypesCLKOUT 27C256 3.5.2Write Bus Cycles27C256 CLKOUT LA15:1 RD LA0 WR BHE A0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WEAD7:0 AD15:8 BUS INTERFACE UNIT3.5.3Interrupt Acknowledge Bus Cycle BUS INTERFACE UNITTable 3-5.Write Cycle Critical Timing Parameters CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCK DT/R DEN A19:16 A15:8 BHE RD, WRT1 T2 T3 T4Processor 3.5.4HALT Bus Cycle CLKOUT 3.5.5Temporarily Exiting the HALT Bus State CLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16CONTROL CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE RFSHBUS INTERFACE UNIT 3.5.6Exiting HALT 3.6SYSTEM DESIGN ALTERNATIVES CLKOUTNMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE RFSH3.6.1Buffering the Data Bus A19:16 3.6.2Synchronizing Software and Hardware Events 3.6.3Using a Locked Bus 3.6.4Using the Queue Status Signals Table 3-7.Queue Status Signal DecodingBUS INTERFACE UNIT 3.7MULTI-MASTERBUS SYSTEM DESIGNS 3.7.1Entering Bus HOLDBUS INTERFACE UNIT Figure 3-33.Queue Status TimingCLKOUT BUS INTERFACE UNIT 3.7.1.2Refresh Operation During a Bus HOLDCLKOUT 3.7.2Exiting HOLD +5 HLDA RESET HOLDPRE DQ CLR Latched HLDA3.8BUS CYCLE PRIORITIES 9.DMA bus cycles Page Peripheral Control Block Page CHAPTER PERIPHERAL CONTROL BLOCK 4.1PERIPHERAL CONTROL REGISTERS4.2PCB RELOCATION REGISTER PCB Relocation Register RELREGRelocates the PCB within memory or I/O space Register NamePERIPHERAL CONTROL BLOCK Table 4-1.Peripheral Control BlockFunction Function4.4ACCESSING THE PERIPHERAL CONTROL BLOCK 4.4.2READY Signals and Wait States4.3RESERVED LOCATIONS 4.4.1Bus Cycles4.4.3F-BusOperation Word readsaddress Byte reads4.5SETTING THE PCB BASE LOCATION 4.4.3.2Accessing the Peripheral Control Registers4.4.3.3Accessing Reserved Locations PERIPHERAL CONTROL BLOCKPage Page Clock Generation and Power Management Page CHAPTER CLOCK GENERATION AND POWER MANAGEMENT 5.1CLOCK GENERATION5.1.1Crystal Oscillator CLOCK GENERATION AND POWER MANAGEMENT Z0 = Inverter Output Z180˚ 5.1.1.1Oscillator OperationFundamental CLOCK GENERATION AND POWER MANAGEMENT Figure 5-4.Equations for Crystal CalculationsCLKOUT Third-OvertoneCrystalCLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2Selecting Crystals5.1.2Using an External Oscillator 5.1.4Reset and Clock Synchronization5.1.3Output from the Clock Generator RESET IN 1µf typical CLOCK GENERATION AND POWER MANAGEMENTFigure 5-5.Simple RC Circuit for Powerup Reset 50 k typicalCLOCK GENERATION AND POWER MANAGEMENT RESETFigure 5-6.Cold Reset Waveform X1 VccCLOCK GENERATION AND POWER MANAGEMENT Figure 5-7.Warm Reset Waveform5.2POWER MANAGEMENT 5.2.1Power-SaveMode CLOCK GENERATION AND POWER MANAGEMENT5.2.1.1Entering Power-SaveMode Register Name Register Mnemonic Register Function Power Save Register PWRSAVEnables and sets clock division factor 0 F F 1 CLOCK GENERATION AND POWER MANAGEMENTCLKOUT WR CLOCK GENERATION AND POWER MANAGEMENTFigure 5-10. Power-SaveClock Transition 5.2.1.2Leaving Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Chip-SelectUnit Page 6.2CHIP-SELECTUNIT FEATURES AND BENEFITS CHAPTER CHIP-SELECTUNIT6.1COMMON METHODS FOR GENERATING CHIP-SELECTS 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEW Chip-SelectsUsingChip-SelectsUsing CHIP-SELECTUNITInternal device EPROM or Flash memory types 1.The chip-selectis enabled 6.4PROGRAMMING 6.4.1Initialization SequenceRegister Name Register MnemonicRegister Function CHIP-SELECTUNITRegister Name Register MnemonicRegister Function CHIP-SELECTUNITRegister Name Register MnemonicRegister Function CHIP-SELECTUNITRegister Name Register MnemonicRegister Function CHIP-SELECTUNITMPCS Register MnemonicCHIP-SELECTUNIT Figure 6-9.MPCS Register Definition6.4.2Programming the Active Ranges Table 6.3 LCS Active Range CHIP-SELECTUNIT 6.4.2.2LCS Active Range6.4.2.3MCS Active Range Table 6-4.MCS Active RangeStarting Address 6.4.3Bus Wait State and Ready Control CHIP-SELECTUNIT 6.4.2.4PCS Active RangeTable 6-6.PCS Active Range 6.4.4Overlapping Chip-Selects BUS READY R2 Control Bit WaitWait State Value R1:0 State Counter READY Wait State Ready6.4.5Memory or I/O Bus Cycle Decoding 6.4.6Programming Considerations6.6.1Example 1: Typical System Configuration CSU Chip Select Device selectExternal Master Chip Select 6.5CHIP-SELECTSAND BUS HOLDCHIP-SELECTUNIT Figure 6-13.Typical SystemCHIP-SELECTUNIT Example 6-1.Initializing the Chip-SelectUnitCHIP-SELECTUNIT CHIP-SELECTUNIT Place memory variables hereRefresh Control Unit Page CHAPTER REFRESH CONTROL UNIT 7.1THE ROLE OF THE REFRESH CONTROL UNIT 7.2REFRESH CONTROL UNIT CAPABILITIES7.3REFRESH CONTROL UNIT OPERATION Refresh Control Unit Operation Set E Bit 7.4REFRESH ADDRESSES REFRESH CONTROL UNITFigure 7-3.Refresh Address Formation 7.5REFRESH BUS CYCLES 7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERSREFRESH CONTROL UNIT Table 7-1.Identification of Refresh Bus CyclesT3/TW 7.7PROGRAMMING THE REFRESH CONTROL UNIT 7.7.1Calculating the Refresh Interval7.7.2Refresh Control Unit Registers REFRESH CONTROL UNITRFBASE Register Name:Refresh Base Address RegisterRegister Mnemonic Refresh Clock Interval Register RFTIMESets refresh rate Register Name7.7.3Programming Example Register Name Register Mnemonic Register FunctionRefresh Control Register RFCON Controls Refresh Unit operationREFRESH CONTROL UNIT Example 7-1.Initializing the Refresh Control Unit7.8REFRESH OPERATION AND BUS HOLD REFRESH CONTROL UNITCLKOUT Page Interrupt Control Unit Page CHAPTER INTERRUPT CONTROL UNIT 8.1FUNCTIONAL OVERVIEW8.2MASTER MODE 8.2.1Generic Functions in Master ModeTable 8-1.Default Interrupt Priorities INTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking8.2.1.2Interrupt Priority Interrupt NameINTERRUPT CONTROL UNIT 8.2.1.3Interrupt Nesting8.3.2Priority Resolution 8.3FUNCTIONAL OPERATION IN MASTER MODE8.3.1Typical Interrupt Sequence •the Interrupt Control Unit has been initialized 8.3.3Cascading with External 8259As INTERRUPT CONTROL UNIT8.3.2.2Interrupts That Share a Single Source INT0 8.3.4Interrupt Acknowledge Sequence 8.3.5PollingINTERRUPT CONTROL UNIT Table 8-2.Fixed Interrupt Types8.3.6Edge and Level Triggering 8.3.7Additional Latency and Response Time8.4PROGRAMMING THE INTERRUPT CONTROL UNIT 8.4.1Interrupt Control Registers INTERRUPT CONTROL UNITRegister Mnemonic: TCUCON, DMA0CON, DMA1CON I2CON, I3CON Register MnemonicI0CON, I1CON Register MnemonicINTERRUPT CONTROL UNIT 8.4.2Interrupt Request Register Interrupt Request RegisterREQST Stores pending interrupt requestsInterrupt Mask Register IMASKMasks individual interrupt sources 8.4.4Priority Mask Register8.4.5In-ServiceRegister Register NamePriority Mask Register Register Mnemonic8.4.6Poll and Poll Status Registers Figure 8-10. In-ServiceRegisterRegister Name Register MnemonicRegister Name Register Mnemonic Register Function Poll Register POLLINTERRUPT CONTROL UNIT Figure 8-11.Poll Register8.4.7End-of-InterruptEOI Register Read to check for pending interrupts when pollingRegister Name Register Mnemonic Register Function Poll Status Register POLLSTS8.4.8Interrupt Status Register Used to issue an EOI commandRegister Name Register Mnemonic Register Function End-of-InterruptRegister EOI8.5SLAVE MODE Register Name Register Mnemonic Register FunctionInterrupt Status Register INTSTS INT0 INTA 80186 Modular Core Select IRQ 8259A82C59A INTA8.5.1Slave Mode Programming INTERRUPT CONTROL UNIT 8.5.1.1Interrupt Vector RegisterTable 8-5.Slave Mode Fixed Interrupt Type Bits INTVEC Register MnemonicINTERRUPT CONTROL UNIT 8.5.1.2End-Of-InterruptRegisterUsed to issue the EOI command Register NameEnd-of-InterruptRegister in Slave Mode Register Mnemonic8.5.2Interrupt Vectoring in Slave Mode Interrupt presented to Interrupt Control Unit INTERRUPT CONTROL UNIT Page Timer/Counter Unit Page CHAPTER TIMER/COUNTER UNIT 9.1FUNCTIONAL OVERVIEWT0 In TIMER/COUNTER UNIT T0INT1IN T0OUT T1OUT TIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow ChartTIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow Chart Continued9.2PROGRAMMING THE TIMER/COUNTER UNIT Maxcount AMaxcount B Dual Maximum Count ModeTimer 0 and 1 Control Registers T0CON, T1CON Defines Timer 0 and 1 operationTIMER/COUNTER UNIT Figure 9-5.Timer 0 and Timer 1 Control RegistersTIMER/COUNTER UNIT Register Name Register Mnemonic Register FunctionTimer 2 Control Register T2CON Defines Timer 2 operationTIMER/COUNTER UNIT Figure 9-6.Timer 2 Control RegisterTimer Count Register Contains the current timer countT0CNT, T1CNT, T2CNT TIMER/COUNTER UNIT9.2.1Initialization Sequence 9.2.2Clock Sources 9.2.3Counting ModesTIMER/COUNTER UNIT Table 9-1.Timer 0 and 1 Clock SourcesTIMER/COUNTER UNIT 9.2.3.1Retriggering9.2.4Pulsed and Variable Duty Cycle Output TIMER/COUNTER UNITTable 9-2.Timer Retriggering 9.2.5Enabling/Disabling Counters Timer Serviced 1Internal Count Value Maxcount -9.2.6Timer Interrupts 9.3.1Input Setup and Hold Timings9.2.7Programming Considerations 9.3TIMING9.3.2Synchronization and Maximum Frequency 9.3.3Real-TimeClock9.3.4Square-WaveGenerator 9.3.5Digital One-ShotTIMER/COUNTER UNIT Example 9-1.Configuring a Real-TimeClockTIMER/COUNTER UNIT TIMER/COUNTER UNIT enable interruptsTIMER/COUNTER UNIT Example 9-2.Configuring a Square-WaveGeneratorTIMER/COUNTER UNIT Example 9-3.Configuring a Digital One-ShotTIMER/COUNTER UNIT Page Direct Memory Access Unit Page CHAPTER DIRECT MEMORY ACCESS UNIT 10.1 FUNCTIONAL OVERVIEW10.1.1 The DMA Transfer Fetch 10.1.2 Source and Destination Pointers 10.1.3 DMA Requests10.1.4 External Requests Fetch Cycle 10.1.5.1Timer 2-InitiatedTransfers 10.1.5 Internal Requests10.1.6 DMA Transfer Counts DIRECT MEMORY ACCESS UNIT10.1.7.1Termination at Terminal Count 10.1.7.2Software Termination10.1.8 DMA Unit Interrupts 10.1.9 DMA Cycles and the BIU10.1.10 The Two-ChannelDMA Unit Module 10.2 PROGRAMMING THE DMA UNIT 10.2.1 DMA Channel ParametersDxSRCH Register Name:DMA Source Address Pointer HighRegister Mnemonic DxSRCL Register Name:DMA Source Address Pointer LowRegister Mnemonic DIRECT MEMORY ACCESS UNIT Register MnemonicDxDSTH Register FunctionDxDSTL Register Name:DMA Destination Address Pointer LowRegister Mnemonic DMA Control Register DxCONControls DMA channel parameters DIRECT MEMORY ACCESS UNITDIRECT MEMORY ACCESS UNIT Register NameDMA Control Register Register MnemonicRegister Name DMA Control RegisterRegister Mnemonic DxCONDIRECT MEMORY ACCESS UNIT 10.2.1.4Arming the DMA Channel10.2.1.5Selecting Channel Synchronization 10.2.1.6Programming the Transfer Count OptionsDMA Transfer Count DxTCContains the DMA channel’s transfer count Register Name10.2.2 Suspension of DMA Transfers 10.2.3 Initializing the DMA Unit10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT 10.3.1 DRQ Pin Timing Requirements10.3.2 DMA Latency 10.3.3 DMA Transfer Rates10.3.4 Generating a DMA Acknowledge 10.4 DMA UNIT EXAMPLESDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA UnitDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedSECTORS DIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA TransfersDIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA Transfers ContinuedPage Math Coprocessing Page CHAPTER MATH COPROCESSING 11.1 OVERVIEW OF MATH COPROCESSING11.2 AVAILABILITY OF MATH COPROCESSING 11.3 THE 80C187 MATH COPROCESSOR 11.3.1 80C187 Instruction Set•the 80C187 uses register or memory operands MATH COPROCESSING Table 11-2.80C187 Arithmetic InstructionsAddition DivisionMATH COPROCESSING 11.3.1.3Comparison Instructions Table 11-3.80C187 Comparison Instructions11.3.1.4Transcendental Instructions Table 11-4.80C187 Transcendental InstructionsMATH COPROCESSING 11.3.1.5Constant Instructions Table 11-5.80C187 Constant Instructions11.3.1.6Processor Control Instructions Table 11-6.80C187 Processor Control Instructions11.3.2 80C187 Data Types 11.4 MICROPROCESSOR AND COPROCESSOR OPERATIONMATH COPROCESSING Figure 11-1. 80C187-SupportedData TypesMATH COPROCESSING 80C187Modular Core11.4.2 Processor Bus Cycles Accessing the 80C187 11.4.1 Clocking the 80C187MATH COPROCESSING Table 11-7.80C187 I/O Port Assignments11.4.3 System Design Tips MATH COPROCESSING 80C187Modular Core11.4.4 Exception Trapping 11.5 EXAMPLE MATH COPROCESSOR ROUTINESMATH COPROCESSING 80C186Modular Core 80C187MATH COPROCESSING MATH COPROCESSING ONCE Mode Page CHAPTER ONCE MODE 12.1 ENTERING/LEAVING ONCE MODEbidirectional weakly held pins except OSCOUT ONCE MODEFigure 12-1.Entering/Leaving ONCE Mode All output80C186 Instruction Set Additions and Extensions Page A.1 80C186 INSTRUCTION SET ADDITIONS A.1.1 Data Transfer InstructionsPUSHA/POPA A.1.2 String Instructions INS source_string, portOUTS port, destination_string A.1.3 High-LevelInstructions1.Main has variables at fixed locations Figure A-2.Variable Access in Nested Procedures 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSFigure A-3.Stack Frame for Main at Level BPA = BP Value for Procedure A Figure A-4.Stack Frame for Procedure A at Level80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BP SP80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BP SPOld BP BPM BPM BPM BPA BPA BPM BPA BPB Display B Dynamic Storage BLEAVE 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSBOUND register, address A.2 80C186 INSTRUCTION SET ENHANCEMENTSA.2.1 Data Transfer Instructions PUSH dataA.2.2 Arithmetic Instructions IMUL destination, source, dataA.2.3 Bit Manipulation Instructions SAL destination, countROL destination, count ROR destination, countRCL destination, count RCR destination, countInput Synchronization Page B.1 WHY SYNCHRONIZERS ARE REQUIRED APPENDIX B INPUT SYNCHRONIZATIONB.2 ASYNCHRONOUS PINS Instruction Set Descriptions Page APPENDIX C INSTRUCTION SET DESCRIPTIONS Table C-1.Instruction Format VariablesINSTRUCTION SET DESCRIPTIONS Table C-2.Instruction OperandsOperand DescriptionINSTRUCTION SET DESCRIPTIONS Table C-3.Flag Bit FunctionsINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction SetINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedADC dest, src INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedName DescriptionCall Procedure CALL procedure-nameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedClear Interrupt-enableFlag INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-10 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-11 INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-12 NameWhen Source Operand is a Byte When Source Operand is a WordINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedProcedure Entry INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-14INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-15 NameWhen Source Operand is a Byte When Source Operand is a WordINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-17 IN accum, portINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-18 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-19 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-20 JA disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJAE disp8 JNB disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJE disp8 JZ disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJL disp8 JGE disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJNE disp8 JNZ disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedJO disp8 JP disp8INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-26 LDS dest, srcLoad Pointer Using ES INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued C-27INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-28 LODS src-stringINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-29 MOV dest, srcINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-30 MOVS dest-string, src-stringINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-31 INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-32 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-33 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-34 INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-35 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-36 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-37 INSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-38 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-39 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedSHL dest, count SAL dest, countINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-41 NameWhen Source Operand is a Byte When Source Operand is a WordINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-43 SHR dest, srcINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-44 STOS dest-stringINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-45 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-46 NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-47 NamePage Instruction Set Opcodes and Clock Cycles Page APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-1.Operand Variables INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set SummaryFunction FormatINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedDATA TRANSFER INSTRUCTIONS Continued ARITHMETIC INSTRUCTIONSINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedARITHMETIC INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedARITHMETIC INSTRUCTIONS Continued BIT MANIPULATION INSTRUCTIONSINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedBIT MANIPULATION INSTRUCTIONS Continued Shifts/RotatesINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedPROGRAM TRANSFER INSTRUCTIONS Continued Iteration ControlINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedTable D-3.Machine Instruction Decoding Guide ByteINSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte BytesINSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES ByteByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Left HalfINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Right HalfD-21 INSTRUCTION SET OPCODES AND CLOCK CYCLES AbbrDefinition AbbrIndex Page INDEX ARDY, See READY ArithmeticINDEX Crystal‚ See OscillatorData bus, See Address and data bus INDEX See also Bus cyclesSee also Refresh Control Unit Index-3INDEX Index-4interrupt INDEX Index-5INDEX Index-6Timers‚ See Timer Counter Unit TCU INDEXIndex-7 INDEX Index-8