Manuals / Intel / Computer Equipment / Computer Hardware

Intel 80C188XL 7.7PROGRAMMING THE REFRESH CONTROL UNIT, 7.7.1Calculating the Refresh Interval

Models: 80C186XL 80C188XL

1 405

Download 405 pages 42.62 Kb

Page 186

7.7PROGRAMMING THE REFRESH CONTROL UNIT

RPERIOD FCPU

REFRESH CONTROL UNIT

7.7PROGRAMMING THE REFRESH CONTROL UNIT

Given a specific processor operating frequency and information about the DRAMs in the system, the user can program the Refresh Control Unit registers.

7.7.1Calculating the Refresh Interval

DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles. (The number of refresh cycles is the same as the num- ber of rows.) You must compensate for bus latency — the time it takes for the Refresh Control Unit to gain control of the bus. This is typically 1–5%, but if an external bus master will be ex- tremely slow to release the bus, increase the overhead percentage. At standard operating frequen- cies, DRAM refresh bus overhead totals 2–3% of the total bus bandwidth.

Given this information and the CPU operating frequency, use the formula in Figure 7-5 to deter- mine the correct value for the RFTIME Register value.

RPERIOD × FCPU

------------------------------------------------------------------------------- = RFTIME RegisterValue

Rows + (Rows × Overhead%)

= Maximum refresh period specified by DRAM manufacturer (in μs). = Operating frequency (in MHz).

Rows = Total number of rows to be refreshed.

Overhead % = Derating factor to compensate for missed refresh requests (typically 1 – 5 %).

Figure 7-5. Formula for Calculating Refresh Interval for RFTIME Register

If the processor enters Power-Save mode, the refresh rate must increase to offset the reduced CPU clock rate to preserve memory. At lower frequencies, the refresh bus overhead increases. At fre- quencies less than about 1.5 MHz, the Bus Interface Unit will spend almost all its time running refresh cycles. There may not be enough bandwidth left for the processor to perform other activ- ities, especially if the processor must share the bus with an external master.

7.7.2Refresh Control Unit Registers

Three contiguous Peripheral Control Block registers operate the Refresh Control Unit: the Re- fresh Base Address Register, Refresh Clock Interval Register and the Refresh Control Register.

7-7

Image 186

Intel 80C188XL 7.7PROGRAMMING THE REFRESH CONTROL UNIT, 7.7.1Calculating the Refresh Interval, Refresh Control Unit

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual 1995Intel Corporation Literature Sales P.O. Box INTRODUCTION CONTENTSCHAPTER CHAPTERCONTENTS CHAPTERBUS INTERFACE UNIT CHAPTER CONTENTSCLOCK GENERATION AND POWER MANAGEMENT PERIPHERAL CONTROL BLOCKREFRESH CONTROL UNIT CONTENTSCHAPTER CHAPTERDIRECT MEMORY ACCESS UNIT CONTENTSTIMER/COUNTER UNIT CHAPTERCONTENTS CHAPTERMATH COPROCESSING ONCE MODE CONTENTSCHAPTER APPENDIX AFIGURES CONTENTSPage Page CONTENTSFIGURES 3-15Page CONTENTSFIGURES 6-11Page CONTENTSFIGURES 10-3TABLES CONTENTSPage Page CONTENTSTABLES D-20Example EXAMPLESCONTENTS PageIntroduction Page CHAPTER INTRODUCTION 1.1HOW TO USE THIS MANUAL INTRODUCTION1.2RELATED DOCUMENTS INTRODUCTIONTable 1-2.Related Documents and Software 1.3.1FaxBack Service 1.3ELECTRONIC SUPPORT SYSTEMS1.3.2Bulletin Board System BBS 1.3.3CompuServe Forums 1.3.4World Wide Web1.4TECHNICAL SUPPORT 1.5PRODUCT LITERATURE 1.6TRAINING CLASSESPage Overview of the 80C186 Family Architecture Page CHAPTER OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1ARCHITECTURAL OVERVIEW 2.1.1Execution Unit OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.2Bus Interface Unit 2.1.3General Registers OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-3.General Registers 2.1.4Segment Registers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-1.Implicit Use of General Registers 2.1.5Instruction Pointer OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREFigure 2-4.Segment Registers 2.1.6Flags 2.1.7Memory Segmentation Register Function Register NameRegister Mnemonic Reset2.1.8Logical Addresses FFFFFH A B D E G J K 0H Data DS Code CS Stack SS Extra ESB E H J C F HOffset 13H Physical Address Offset 3H Segment Base LogicalAddresses Segment Base 2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH2.1.9Dynamically Relocatable Code OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-2.Logical Address Sources Before 2.1.10 Stack Implementation 2.1.11 Reserved Memory and I/O SpaceOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-10.Stack Operation2.2SOFTWARE OVERVIEW 2.2.1Instruction SetTable 2-3.Data Transfer Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.1Data Transfer Instructions General-PurposeFigure 2-11.Flag Storage Format I = Interrupt Enable Flag T = Trap FlagOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.2Arithmetic InstructionsAddition OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-4.Arithmetic Instructions SubtractionTable 2-6.Bit Manipulation Instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.3Bit Manipulation Instructions Bit PatternOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.4String InstructionsTable 2-7.String Instructions SI DI CX AL/AX DF ZF OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.2.1.5Program Transfer Instructions Scan value Destination for LODS Source for STOSUnconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers Conditional Transfers OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-9.Program Transfer Instructions Unconditional TransfersCondition Tested OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREMnemonic “Jump if…”2.2.1.6Processor Control Instructions 2.2.2Addressing ModesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-11.Processor Control InstructionsOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2.2Memory Addressing ModesEncoded in the Instruction Explicit in the Mod R/M DisplacementOpcode OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREMod R/M DisplacementOpcode BX or BPDisplacement Opcode Mod R/M DisplacementOpcode BX or BPHigh Address Opcode Data Opcode SI DISource EA Destination EA Port Address Direct Port AddressingType OVERVIEW OF THE 80C186 FAMILY ARCHITECTURETable 2-12.Supported Data Types DescriptionOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Control Unit NMI CPUMaskable Interrupt Request Interrupt Acknowledge External Interrupt SourcesOVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Figure 2-25.Interrupt Vector Table3.The current CS and IP are pushed onto the stack Stack PSW OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Divide Error — TypeSingle Step — Type 2.3.1.2Maskable InterruptsInterrupt on Overflow — Type Numerics Coprocessor Fault — TypeBreakpoint Interrupt — Type Array Bounds Check — Type2.3.2Software Interrupts 2.3.3Interrupt LatencyTotal 2.3.4Interrupt Response TimeClocks 2.3.5Interrupt and Exception PriorityService Routine IRET Execute Divide Divide ErrorPush PSW, CS, IP Fetch Divide Error Vector Service Routine IRETNMI Instruction Push PSW, CS, IP Fetch Divide Error VectorService Routine IRET Trap Flag = ??? Trap Flag =Interrupt Enable Bit IE = Trap Flag TF = Page Bus Interface Unit Page 3.2ADDRESS AND DATA BUS CONCEPTS CHAPTER BUS INTERFACE UNIT3.1MULTIPLEXED ADDRESS AND DATA BUS 3.2.116-BitData Bus1 MByte 512 KBytes512 KBytes Even Byte Transfer Odd Byte TransferD7:0 A0 Low A19D15 8 BHE BUS INTERFACE UNITFirst Bus Cycle Second Bus Cycle3.2.28-BitData Bus 3.3MEMORY AND I/O INTERFACES A19:0D7:0 First Bus Cycle3.3.116-BitBus Memory and I/O Requirements 3.3.28-BitBus Memory and I/O Requirements3.4BUS CYCLE OPERATION Falling PhaseCLKOUT RisingBus Ready 3.4.1Address/Status Phase or TI Signals From CPU 3.4.2Data Phase 3.4.3Wait Statesor TW T1 T2 T3 TW TW T4 CLKOUT Clear Clock CS1 CS2 CS3 CS4 ALE CLKOUTWait State Module Input Input READYREADY Wait State Module CS1 Enable CS2Load CLKOUT3.4.4Idle States CLKOUTARDY SRDY •The instruction prefetch queue is full BUS INTERFACE UNIT 3.5BUS CYCLES3.5.1Read Bus Cycles Table 3-2. Read Bus Cycle TypesCLKOUT 27C256 3.5.2Write Bus Cycles27C256 CLKOUT AD7:0 AD15:8 LA15:1 RD LA0 WR BHEA0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WE BUS INTERFACE UNIT3.5.3Interrupt Acknowledge Bus Cycle BUS INTERFACE UNITTable 3-5.Write Cycle Critical Timing Parameters T1 T2 CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCKDT/R DEN A19:16 A15:8 BHE RD, WR T3 T4Processor 3.5.4HALT Bus Cycle CLKOUT 3.5.5Temporarily Exiting the HALT Bus State CLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16CONTROL CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE RFSHBUS INTERFACE UNIT 3.5.6Exiting HALT NMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE 3.6SYSTEM DESIGN ALTERNATIVESCLKOUT RFSH3.6.1Buffering the Data Bus A19:16 3.6.2Synchronizing Software and Hardware Events 3.6.3Using a Locked Bus 3.6.4Using the Queue Status Signals Table 3-7.Queue Status Signal DecodingBUS INTERFACE UNIT BUS INTERFACE UNIT 3.7MULTI-MASTERBUS SYSTEM DESIGNS3.7.1Entering Bus HOLD Figure 3-33.Queue Status TimingCLKOUT BUS INTERFACE UNIT 3.7.1.2Refresh Operation During a Bus HOLDCLKOUT PRE DQ CLR 3.7.2Exiting HOLD+5 HLDA RESET HOLD Latched HLDA3.8BUS CYCLE PRIORITIES 9.DMA bus cycles Page Peripheral Control Block Page CHAPTER PERIPHERAL CONTROL BLOCK 4.1PERIPHERAL CONTROL REGISTERS4.2PCB RELOCATION REGISTER Relocates the PCB within memory or I/O space PCB Relocation RegisterRELREG Register NameFunction PERIPHERAL CONTROL BLOCKTable 4-1.Peripheral Control Block Function4.3RESERVED LOCATIONS 4.4ACCESSING THE PERIPHERAL CONTROL BLOCK4.4.2READY Signals and Wait States 4.4.1Bus Cyclesaddress 4.4.3F-BusOperationWord reads Byte reads4.4.3.3Accessing Reserved Locations 4.5SETTING THE PCB BASE LOCATION4.4.3.2Accessing the Peripheral Control Registers PERIPHERAL CONTROL BLOCKPage Page Clock Generation and Power Management Page CHAPTER CLOCK GENERATION AND POWER MANAGEMENT 5.1CLOCK GENERATION5.1.1Crystal Oscillator 180˚ CLOCK GENERATION AND POWER MANAGEMENTZ0 = Inverter Output Z 5.1.1.1Oscillator OperationFundamental CLKOUT CLOCK GENERATION AND POWER MANAGEMENTFigure 5-4.Equations for Crystal Calculations Third-OvertoneCrystalCLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2Selecting Crystals5.1.2Using an External Oscillator 5.1.4Reset and Clock Synchronization5.1.3Output from the Clock Generator Figure 5-5.Simple RC Circuit for Powerup Reset RESET IN 1µf typicalCLOCK GENERATION AND POWER MANAGEMENT 50 k typicalFigure 5-6.Cold Reset Waveform CLOCK GENERATION AND POWER MANAGEMENTRESET X1 VccCLOCK GENERATION AND POWER MANAGEMENT Figure 5-7.Warm Reset Waveform5.2POWER MANAGEMENT 5.2.1Power-SaveMode CLOCK GENERATION AND POWER MANAGEMENT5.2.1.1Entering Power-SaveMode Enables and sets clock division factor 0 F F 1 Register Name Register Mnemonic Register FunctionPower Save Register PWRSAV CLOCK GENERATION AND POWER MANAGEMENTFigure 5-10. Power-SaveClock Transition CLKOUT WRCLOCK GENERATION AND POWER MANAGEMENT 5.2.1.2Leaving Power-SaveModeCLOCK GENERATION AND POWER MANAGEMENT Chip-SelectUnit Page 6.2CHIP-SELECTUNIT FEATURES AND BENEFITS CHAPTER CHIP-SELECTUNIT6.1COMMON METHODS FOR GENERATING CHIP-SELECTS Chip-SelectsUsing 6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEWChip-SelectsUsing CHIP-SELECTUNITInternal device EPROM or Flash memory types 1.The chip-selectis enabled 6.4PROGRAMMING 6.4.1Initialization SequenceRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITRegister Function Register NameRegister Mnemonic CHIP-SELECTUNITCHIP-SELECTUNIT MPCSRegister Mnemonic Figure 6-9.MPCS Register Definition6.4.2Programming the Active Ranges 6.4.2.3MCS Active Range Table 6.3 LCS Active RangeCHIP-SELECTUNIT 6.4.2.2LCS Active Range Table 6-4.MCS Active RangeStarting Address 6.4.3Bus Wait State and Ready Control CHIP-SELECTUNIT 6.4.2.4PCS Active RangeTable 6-6.PCS Active Range Wait State Value R1:0 State Counter 6.4.4Overlapping Chip-SelectsBUS READY R2 Control Bit Wait READY Wait State Ready6.4.5Memory or I/O Bus Cycle Decoding 6.4.6Programming ConsiderationsExternal Master Chip Select 6.6.1Example 1: Typical System ConfigurationCSU Chip Select Device select 6.5CHIP-SELECTSAND BUS HOLDCHIP-SELECTUNIT Figure 6-13.Typical SystemCHIP-SELECTUNIT Example 6-1.Initializing the Chip-SelectUnitCHIP-SELECTUNIT CHIP-SELECTUNIT Place memory variables hereRefresh Control Unit Page CHAPTER REFRESH CONTROL UNIT 7.1THE ROLE OF THE REFRESH CONTROL UNIT 7.2REFRESH CONTROL UNIT CAPABILITIES7.3REFRESH CONTROL UNIT OPERATION Refresh Control Unit Operation Set E Bit 7.4REFRESH ADDRESSES REFRESH CONTROL UNITFigure 7-3.Refresh Address Formation REFRESH CONTROL UNIT 7.5REFRESH BUS CYCLES7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERS Table 7-1.Identification of Refresh Bus CyclesT3/TW 7.7.2Refresh Control Unit Registers 7.7PROGRAMMING THE REFRESH CONTROL UNIT7.7.1Calculating the Refresh Interval REFRESH CONTROL UNITRFBASE Register Name:Refresh Base Address RegisterRegister Mnemonic Sets refresh rate Refresh Clock Interval RegisterRFTIME Register NameRefresh Control Register RFCON 7.7.3Programming ExampleRegister Name Register Mnemonic Register Function Controls Refresh Unit operationREFRESH CONTROL UNIT Example 7-1.Initializing the Refresh Control Unit7.8REFRESH OPERATION AND BUS HOLD REFRESH CONTROL UNITCLKOUT Page Interrupt Control Unit Page CHAPTER INTERRUPT CONTROL UNIT 8.1FUNCTIONAL OVERVIEW8.2MASTER MODE 8.2.1Generic Functions in Master Mode8.2.1.2Interrupt Priority Table 8-1.Default Interrupt PrioritiesINTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking Interrupt NameINTERRUPT CONTROL UNIT 8.2.1.3Interrupt Nesting8.3.2Priority Resolution 8.3FUNCTIONAL OPERATION IN MASTER MODE8.3.1Typical Interrupt Sequence •the Interrupt Control Unit has been initialized 8.3.3Cascading with External 8259As INTERRUPT CONTROL UNIT8.3.2.2Interrupts That Share a Single Source INT0 INTERRUPT CONTROL UNIT 8.3.4Interrupt Acknowledge Sequence8.3.5Polling Table 8-2.Fixed Interrupt Types8.3.6Edge and Level Triggering 8.3.7Additional Latency and Response Time8.4PROGRAMMING THE INTERRUPT CONTROL UNIT 8.4.1Interrupt Control Registers INTERRUPT CONTROL UNITRegister Mnemonic: TCUCON, DMA0CON, DMA1CON I2CON, I3CON Register MnemonicI0CON, I1CON Register MnemonicINTERRUPT CONTROL UNIT REQST 8.4.2Interrupt Request RegisterInterrupt Request Register Stores pending interrupt requestsMasks individual interrupt sources Interrupt Mask RegisterIMASK 8.4.4Priority Mask RegisterPriority Mask Register 8.4.5In-ServiceRegisterRegister Name Register MnemonicRegister Name 8.4.6Poll and Poll Status RegistersFigure 8-10. In-ServiceRegister Register MnemonicINTERRUPT CONTROL UNIT Register Name Register Mnemonic Register FunctionPoll Register POLL Figure 8-11.Poll RegisterRegister Name Register Mnemonic Register Function 8.4.7End-of-InterruptEOI RegisterRead to check for pending interrupts when polling Poll Status Register POLLSTSRegister Name Register Mnemonic Register Function 8.4.8Interrupt Status RegisterUsed to issue an EOI command End-of-InterruptRegister EOI8.5SLAVE MODE Register Name Register Mnemonic Register FunctionInterrupt Status Register INTSTS 82C59A INT0 INTA 80186 Modular Core Select IRQ8259A INTA8.5.1Slave Mode Programming INTERRUPT CONTROL UNIT 8.5.1.1Interrupt Vector RegisterTable 8-5.Slave Mode Fixed Interrupt Type Bits INTERRUPT CONTROL UNIT INTVECRegister Mnemonic 8.5.1.2End-Of-InterruptRegisterEnd-of-InterruptRegister in Slave Mode Used to issue the EOI commandRegister Name Register Mnemonic8.5.2Interrupt Vectoring in Slave Mode Interrupt presented to Interrupt Control Unit INTERRUPT CONTROL UNIT Page Timer/Counter Unit Page CHAPTER TIMER/COUNTER UNIT 9.1FUNCTIONAL OVERVIEWT0 In TIMER/COUNTER UNIT T0INT1IN T0OUT T1OUT TIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow ChartTIMER/COUNTER UNIT Figure 9-3.Timers 0 and 1 Flow Chart ContinuedMaxcount B 9.2PROGRAMMING THE TIMER/COUNTER UNITMaxcount A Dual Maximum Count ModeTIMER/COUNTER UNIT Timer 0 and 1 Control Registers T0CON, T1CONDefines Timer 0 and 1 operation Figure 9-5.Timer 0 and Timer 1 Control RegistersTIMER/COUNTER UNIT Register Name Register Mnemonic Register FunctionTIMER/COUNTER UNIT Timer 2 Control Register T2CONDefines Timer 2 operation Figure 9-6.Timer 2 Control RegisterT0CNT, T1CNT, T2CNT Timer Count RegisterContains the current timer count TIMER/COUNTER UNIT9.2.1Initialization Sequence TIMER/COUNTER UNIT 9.2.2Clock Sources9.2.3Counting Modes Table 9-1.Timer 0 and 1 Clock SourcesTIMER/COUNTER UNIT 9.2.3.1Retriggering9.2.4Pulsed and Variable Duty Cycle Output TIMER/COUNTER UNITTable 9-2.Timer Retriggering Internal Count Value 9.2.5Enabling/Disabling CountersTimer Serviced 1 Maxcount -9.2.7Programming Considerations 9.2.6Timer Interrupts9.3.1Input Setup and Hold Timings 9.3TIMING9.3.4Square-WaveGenerator 9.3.2Synchronization and Maximum Frequency9.3.3Real-TimeClock 9.3.5Digital One-ShotTIMER/COUNTER UNIT Example 9-1.Configuring a Real-TimeClockTIMER/COUNTER UNIT TIMER/COUNTER UNIT enable interruptsTIMER/COUNTER UNIT Example 9-2.Configuring a Square-WaveGeneratorTIMER/COUNTER UNIT Example 9-3.Configuring a Digital One-ShotTIMER/COUNTER UNIT Page Direct Memory Access Unit Page CHAPTER DIRECT MEMORY ACCESS UNIT 10.1 FUNCTIONAL OVERVIEW10.1.1 The DMA Transfer Fetch 10.1.2 Source and Destination Pointers 10.1.3 DMA Requests10.1.4 External Requests Fetch Cycle 10.1.5.1Timer 2-InitiatedTransfers 10.1.5 Internal Requests10.1.7.1Termination at Terminal Count 10.1.6 DMA Transfer CountsDIRECT MEMORY ACCESS UNIT 10.1.7.2Software Termination10.1.8 DMA Unit Interrupts 10.1.9 DMA Cycles and the BIU10.1.10 The Two-ChannelDMA Unit Module 10.2 PROGRAMMING THE DMA UNIT 10.2.1 DMA Channel ParametersDxSRCH Register Name:DMA Source Address Pointer HighRegister Mnemonic DxSRCL Register Name:DMA Source Address Pointer LowRegister Mnemonic DxDSTH DIRECT MEMORY ACCESS UNITRegister Mnemonic Register FunctionDxDSTL Register Name:DMA Destination Address Pointer LowRegister Mnemonic Controls DMA channel parameters DMA Control RegisterDxCON DIRECT MEMORY ACCESS UNITDMA Control Register DIRECT MEMORY ACCESS UNITRegister Name Register MnemonicRegister Mnemonic Register NameDMA Control Register DxCON10.2.1.5Selecting Channel Synchronization DIRECT MEMORY ACCESS UNIT10.2.1.4Arming the DMA Channel 10.2.1.6Programming the Transfer Count OptionsContains the DMA channel’s transfer count DMA Transfer CountDxTC Register Name10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT 10.2.2 Suspension of DMA Transfers10.2.3 Initializing the DMA Unit 10.3.1 DRQ Pin Timing Requirements10.3.2 DMA Latency 10.3.3 DMA Transfer Rates10.3.4 Generating a DMA Acknowledge 10.4 DMA UNIT EXAMPLESDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA UnitDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedDIRECT MEMORY ACCESS UNIT Example 10-1.Initializing the DMA Unit ContinuedSECTORS DIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA TransfersDIRECT MEMORY ACCESS UNIT Example 10-2.Timed DMA Transfers ContinuedPage Math Coprocessing Page CHAPTER MATH COPROCESSING 11.1 OVERVIEW OF MATH COPROCESSING11.2 AVAILABILITY OF MATH COPROCESSING 11.3 THE 80C187 MATH COPROCESSOR 11.3.1 80C187 Instruction Set•the 80C187 uses register or memory operands Addition MATH COPROCESSINGTable 11-2.80C187 Arithmetic Instructions Division11.3.1.4Transcendental Instructions MATH COPROCESSING 11.3.1.3Comparison InstructionsTable 11-3.80C187 Comparison Instructions Table 11-4.80C187 Transcendental Instructions11.3.1.6Processor Control Instructions MATH COPROCESSING 11.3.1.5Constant InstructionsTable 11-5.80C187 Constant Instructions Table 11-6.80C187 Processor Control Instructions11.3.2 80C187 Data Types 11.4 MICROPROCESSOR AND COPROCESSOR OPERATIONMATH COPROCESSING Figure 11-1. 80C187-SupportedData TypesModular MATH COPROCESSING80C187 CoreMATH COPROCESSING 11.4.2 Processor Bus Cycles Accessing the 80C18711.4.1 Clocking the 80C187 Table 11-7.80C187 I/O Port Assignments11.4.3 System Design Tips Modular MATH COPROCESSING80C187 Core11.4.4 Exception Trapping 11.5 EXAMPLE MATH COPROCESSOR ROUTINESModular Core MATH COPROCESSING80C186 80C187MATH COPROCESSING MATH COPROCESSING ONCE Mode Page CHAPTER ONCE MODE 12.1 ENTERING/LEAVING ONCE MODEFigure 12-1.Entering/Leaving ONCE Mode bidirectional weakly held pins except OSCOUTONCE MODE All output80C186 Instruction Set Additions and Extensions Page A.1 80C186 INSTRUCTION SET ADDITIONS A.1.1 Data Transfer InstructionsPUSHA/POPA OUTS port, destination_string A.1.2 String InstructionsINS source_string, port A.1.3 High-LevelInstructions1.Main has variables at fixed locations Figure A-2.Variable Access in Nested Procedures 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSFigure A-3.Stack Frame for Main at Level 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BPA = BP Value for Procedure AFigure A-4.Stack Frame for Procedure A at Level BP SPOld BP BPM BPM BPM BPA BPA BPM BPA BPB 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSBP SP Display B Dynamic Storage BLEAVE 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSA.2.1 Data Transfer Instructions BOUND register, addressA.2 80C186 INSTRUCTION SET ENHANCEMENTS PUSH dataA.2.3 Bit Manipulation Instructions A.2.2 Arithmetic InstructionsIMUL destination, source, data SAL destination, countRCL destination, count ROL destination, countROR destination, count RCR destination, countInput Synchronization Page B.1 WHY SYNCHRONIZERS ARE REQUIRED APPENDIX B INPUT SYNCHRONIZATIONB.2 ASYNCHRONOUS PINS Instruction Set Descriptions Page APPENDIX C INSTRUCTION SET DESCRIPTIONS Table C-1.Instruction Format VariablesOperand INSTRUCTION SET DESCRIPTIONSTable C-2.Instruction Operands DescriptionINSTRUCTION SET DESCRIPTIONS Table C-3.Flag Bit FunctionsINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction SetINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedADC dest, src Name INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued DescriptionINSTRUCTION SET DESCRIPTIONS Call ProcedureCALL procedure-name Table C-4.Instruction Set ContinuedINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued Clear Interrupt-enableFlagINSTRUCTION SET DESCRIPTIONS NameC-10 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-11 C-12 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS When Source Operand is a ByteWhen Source Operand is a Word Table C-4.Instruction Set ContinuedTable C-4.Instruction Set Continued Procedure EntryINSTRUCTION SET DESCRIPTIONS C-14C-15 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS When Source Operand is a ByteWhen Source Operand is a Word Table C-4.Instruction Set ContinuedC-17 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued IN accum, portC-18 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-19 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-20 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JA disp8JAE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JNB disp8JE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JZ disp8JL disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JGE disp8JNE disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JNZ disp8JO disp8 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued JP disp8C-26 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued LDS dest, srcTable C-4.Instruction Set Continued Load Pointer Using ESINSTRUCTION SET DESCRIPTIONS C-27C-28 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued LODS src-stringC-29 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued MOV dest, srcC-30 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued MOVS dest-string, src-stringINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-31 C-32 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-33 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-34 C-35 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-36 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS Table C-4.Instruction Set ContinuedC-37 C-38 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-39 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameSHL dest, count INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued SAL dest, countC-41 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameINSTRUCTION SET DESCRIPTIONS When Source Operand is a ByteWhen Source Operand is a Word Table C-4.Instruction Set ContinuedC-43 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued SHR dest, srcC-44 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued STOS dest-stringC-45 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-46 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NameC-47 INSTRUCTION SET DESCRIPTIONSTable C-4.Instruction Set Continued NamePage Instruction Set Opcodes and Clock Cycles Page APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-1.Operand Variables Function INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary FormatDATA TRANSFER INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued ARITHMETIC INSTRUCTIONSINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedARITHMETIC INSTRUCTIONS Continued ARITHMETIC INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued BIT MANIPULATION INSTRUCTIONSBIT MANIPULATION INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued Shifts/RotatesINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.Instruction Set Summary ContinuedPROGRAM TRANSFER INSTRUCTIONS Continued INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued Iteration ControlTable D-3.Machine Instruction Decoding Guide INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-2.Instruction Set Summary Continued ByteByte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte BytesByte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6Byte INSTRUCTION SET OPCODES AND CLOCK CYCLESByte Bytes 3–6INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Left HalfINSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.Mnemonic Encoding Matrix Right HalfD-21 Definition INSTRUCTION SET OPCODES AND CLOCK CYCLESAbbr AbbrIndex Page INDEX ARDY, See READY ArithmeticINDEX Crystal‚ See OscillatorData bus, See Address and data bus See also Refresh Control Unit INDEXSee also Bus cycles Index-3INDEX Index-4interrupt INDEX Index-5INDEX Index-6Timers‚ See Timer Counter Unit TCU INDEXIndex-7 INDEX Index-8