Intel 80C188XL, 80C186XL Programming the Refresh Control Unit, Calculating the Refresh Interval

RPERIOD FCPU

REFRESH CONTROL UNIT

7.7PROGRAMMING THE REFRESH CONTROL UNIT

Given a specific processor operating frequency and information about the DRAMs in the system, the user can program the Refresh Control Unit registers.

7.7.1Calculating the Refresh Interval

DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles. (The number of refresh cycles is the same as the num- ber of rows.) You must compensate for bus latency — the time it takes for the Refresh Control Unit to gain control of the bus. This is typically 1–5%, but if an external bus master will be ex- tremely slow to release the bus, increase the overhead percentage. At standard operating frequen- cies, DRAM refresh bus overhead totals 2–3% of the total bus bandwidth.

Given this information and the CPU operating frequency, use the formula in Figure 7-5 to deter- mine the correct value for the RFTIME Register value.

RPERIOD × FCPU

------------------------------------------------------------------------------- = RFTIME RegisterValue

Rows + (Rows × Overhead%)

= Maximum refresh period specified by DRAM manufacturer (in μs). = Operating frequency (in MHz).

Rows = Total number of rows to be refreshed.

Overhead % = Derating factor to compensate for missed refresh requests (typically 1 – 5 %).

Figure 7-5. Formula for Calculating Refresh Interval for RFTIME Register

If the processor enters Power-Save mode, the refresh rate must increase to offset the reduced CPU clock rate to preserve memory. At lower frequencies, the refresh bus overhead increases. At fre- quencies less than about 1.5 MHz, the Bus Interface Unit will spend almost all its time running refresh cycles. There may not be enough bandwidth left for the processor to perform other activ- ities, especially if the processor must share the bus with an external master.

7.7.2Refresh Control Unit Registers

Three contiguous Peripheral Control Block registers operate the Refresh Control Unit: the Re- fresh Base Address Register, Refresh Clock Interval Register and the Refresh Control Register.

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