80C186XL/80C188XL Microprocessor User’s Manual
1995
80C186XL/80C188XL Microprocessor User’s Manual
Intel Corporation Literature Sales P.O. Box
CHAPTER
CONTENTS
CHAPTER
INTRODUCTION
BUS INTERFACE UNIT
CONTENTS
CHAPTER
PERIPHERAL CONTROL BLOCK
CONTENTS
CLOCK GENERATION AND POWER MANAGEMENT
CHAPTER
CHAPTER
CONTENTS
CHAPTER
REFRESH CONTROL UNIT
CHAPTER
CONTENTS
TIMER/COUNTER UNIT
DIRECT MEMORY ACCESS UNIT
MATH COPROCESSING
CONTENTS
CHAPTER
APPENDIX A
CONTENTS
CHAPTER
ONCE MODE
Page
FIGURES
CONTENTS
3-15
CONTENTS
FIGURES
Page
6-11
CONTENTS
FIGURES
Page
10-3
CONTENTS
FIGURES
Page
Page
TABLES
CONTENTS
D-20
CONTENTS
TABLES
Page
Page
EXAMPLES
CONTENTS
Example
Introduction
Page
CHAPTER INTRODUCTION
INTRODUCTION
1.1HOW TO USE THIS MANUAL
Table 1-2.Related Documents and Software
1.2RELATED DOCUMENTS
INTRODUCTION
1.3ELECTRONIC SUPPORT SYSTEMS
1.3.1FaxBack Service
1.3.2Bulletin Board System BBS
1.4TECHNICAL SUPPORT
1.3.3CompuServe Forums
1.3.4World Wide Web
1.6TRAINING CLASSES
1.5PRODUCT LITERATURE
Page
Overview of the 80C186 Family Architecture
Page
2.1ARCHITECTURAL OVERVIEW
CHAPTER OVERVIEW OF THE 80C186 FAMILY
ARCHITECTURE
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.1Execution Unit
2.1.2Bus Interface Unit
Figure 2-3.General Registers
2.1.3General Registers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-1.Implicit Use of General Registers
2.1.4Segment Registers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-4.Segment Registers
2.1.5Instruction Pointer
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1.6Flags
2.1.7Memory Segmentation
Reset
Register Name
Register Mnemonic
Register Function
2.1.8Logical Addresses
C F H
Data DS Code CS Stack SS Extra ES
B E H J
FFFFFH A B D E G J K 0H
2C4H 2C3H 2C2H 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH
Physical Address Offset 3H Segment Base Logical
Addresses Segment Base
Offset 13H
Table 2-2.Logical Address Sources
2.1.9Dynamically Relocatable Code
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Before
2.1.11 Reserved Memory and I/O Space
2.1.10 Stack Implementation
Figure 2-10.Stack Operation
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1Instruction Set
2.2SOFTWARE OVERVIEW
General-Purpose
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.1Data Transfer Instructions
Table 2-3.Data Transfer Instructions
2.2.1.2Arithmetic Instructions
I = Interrupt Enable Flag T = Trap Flag
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Figure 2-11.Flag Storage Format
Subtraction
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-4.Arithmetic Instructions
Addition
Bit Pattern
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.3Bit Manipulation Instructions
Table 2-6.Bit Manipulation Instructions
Table 2-7.String Instructions
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.4String Instructions
Scan value Destination for LODS Source for STOS
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.5Program Transfer Instructions
SI DI CX AL/AX DF ZF
Unconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans- fer. The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers
Unconditional Transfers
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-9.Program Transfer Instructions
Conditional Transfers
“Jump if…”
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Mnemonic
Condition Tested
Table 2-11.Processor Control Instructions
2.2.2Addressing Modes
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.2.1.6Processor Control Instructions
2.2.2.2Memory Addressing Modes
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Encoded in the Instruction Explicit in the
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Displacement
Opcode
Mod R/M
BX or BP
Displacement
Opcode
Mod R/M
Displacement
Opcode
BX or BP
Displacement
Opcode
Mod R/M
High Address
Port Address Direct Port Addressing
Opcode SI DI
Source EA Destination EA
Opcode Data
Description
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Table 2-12.Supported Data Types
Type
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
External Interrupt Sources
NMI CPU
Maskable Interrupt Request Interrupt Acknowledge
Interrupt Control Unit
Figure 2-25.Interrupt Vector Table
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
3.The current CS and IP are pushed onto the stack
Stack PSW
2.3.1.2Maskable Interrupts
Divide Error — Type
Single Step — Type
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Array Bounds Check — Type
Numerics Coprocessor Fault — Type
Breakpoint Interrupt — Type
Interrupt on Overflow — Type
2.3.3Interrupt Latency
2.3.2Software Interrupts
2.3.5Interrupt and Exception Priority
2.3.4Interrupt Response Time
Clocks
Total
Service Routine IRET
Divide Error
Push PSW, CS, IP Fetch Divide Error Vector
Service Routine IRET Execute Divide
Trap Flag =
Push PSW, CS, IP Fetch Divide Error Vector
Service Routine IRET Trap Flag = ???
NMI Instruction
Interrupt Enable Bit IE = Trap Flag TF =
Page
Bus Interface Unit
Page
3.2.116-BitData Bus
CHAPTER BUS INTERFACE UNIT
3.1MULTIPLEXED ADDRESS AND DATA BUS
3.2ADDRESS AND DATA BUS CONCEPTS
512 KBytes
1 MByte
512 KBytes
Odd Byte Transfer
Even Byte Transfer
BUS INTERFACE UNIT
A19
D15 8 BHE
D7:0 A0 Low
3.2.28-BitData Bus
First Bus Cycle
Second Bus Cycle
First Bus Cycle
A19:0
D7:0
3.3MEMORY AND I/O INTERFACES
3.4BUS CYCLE OPERATION
3.3.116-BitBus Memory and I/O Requirements
3.3.28-BitBus Memory and I/O Requirements
Rising
Phase
CLKOUT
Falling
Bus Ready
3.4.1Address/Status Phase
or TI
Signals From CPU
3.4.3Wait States
3.4.2Data Phase
or TW
T1 T2 T3 TW TW T4 CLKOUT
READY
CS1 CS2 CS3 CS4 ALE CLKOUT
Wait State Module Input Input
Clear Clock
CLKOUT
Wait State Module CS1 Enable CS2
Load
READY
ARDY SRDY
3.4.4Idle States
CLKOUT
•The instruction prefetch queue is full
Table 3-2. Read Bus Cycle Types
3.5BUS CYCLES
3.5.1Read Bus Cycles
BUS INTERFACE UNIT
CLKOUT
27C256
27C256
3.5.2Write Bus Cycles
CLKOUT
BUS INTERFACE UNIT
LA15:1 RD LA0 WR BHE
A0:14 OE I/O1:8 WE CS1 A0:14 OE I/O1:8 WE
AD7:0 AD15:8
Table 3-5.Write Cycle Critical Timing Parameters
3.5.3Interrupt Acknowledge Bus Cycle
BUS INTERFACE UNIT
T3 T4
CLKOUT ALE S2:0 INTA0 INTA1 AD15:0 AD7:0 LOCK
DT/R DEN A19:16 A15:8 BHE RD, WR
T1 T2
Processor
3.5.4HALT Bus Cycle
CLKOUT
CONTROL
3.5.5Temporarily Exiting the HALT Bus State
CLKOUT HOLD HLDA AD15:0 AD7:0 A15:8 A19:16
BUS INTERFACE UNIT
CLKOUT ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE
RFSH
3.5.6Exiting HALT
RFSH
3.6SYSTEM DESIGN ALTERNATIVES
CLKOUT
NMI/INTx ALE S2:0 AD15:0 AD7:0 A15:8 A19:16 BHE
3.6.1Buffering the Data Bus
A19:16
3.6.2Synchronizing Software and Hardware Events
3.6.3Using a Locked Bus
BUS INTERFACE UNIT
3.6.4Using the Queue Status Signals
Table 3-7.Queue Status Signal Decoding
Figure 3-33.Queue Status Timing
3.7MULTI-MASTERBUS SYSTEM DESIGNS
3.7.1Entering Bus HOLD
BUS INTERFACE UNIT
CLKOUT
3.7.1.2Refresh Operation During a Bus HOLD
BUS INTERFACE UNIT
CLKOUT
Latched HLDA
3.7.2Exiting HOLD
+5 HLDA RESET HOLD
PRE DQ CLR
3.8BUS CYCLE PRIORITIES
9.DMA bus cycles
Page
Peripheral Control Block
Page
4.2PCB RELOCATION REGISTER
CHAPTER PERIPHERAL CONTROL BLOCK
4.1PERIPHERAL CONTROL REGISTERS
Register Name
PCB Relocation Register
RELREG
Relocates the PCB within memory or I/O space
Function
PERIPHERAL CONTROL BLOCK
Table 4-1.Peripheral Control Block
Function
4.4.1Bus Cycles
4.4ACCESSING THE PERIPHERAL CONTROL BLOCK
4.4.2READY Signals and Wait States
4.3RESERVED LOCATIONS
Byte reads
4.4.3F-BusOperation
Word reads
address
PERIPHERAL CONTROL BLOCK
4.5SETTING THE PCB BASE LOCATION
4.4.3.2Accessing the Peripheral Control Registers
4.4.3.3Accessing Reserved Locations
Page
Page
Clock Generation and Power Management
Page
5.1.1Crystal Oscillator
CHAPTER CLOCK GENERATION AND POWER MANAGEMENT
5.1CLOCK GENERATION
5.1.1.1Oscillator Operation
CLOCK GENERATION AND POWER MANAGEMENT
Z0 = Inverter Output Z
180˚
Fundamental
Third-OvertoneCrystal
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-4.Equations for Crystal Calculations
CLKOUT
5.1.1.2Selecting Crystals
CLOCK GENERATION AND POWER MANAGEMENT
5.1.3Output from the Clock Generator
5.1.2Using an External Oscillator
5.1.4Reset and Clock Synchronization
50 k typical
RESET IN 1µf typical
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-5.Simple RC Circuit for Powerup Reset
X1 Vcc
CLOCK GENERATION AND POWER MANAGEMENT
RESET
Figure 5-6.Cold Reset Waveform
Figure 5-7.Warm Reset Waveform
CLOCK GENERATION AND POWER MANAGEMENT
5.2POWER MANAGEMENT
5.2.1.1Entering Power-SaveMode
5.2.1Power-SaveMode
CLOCK GENERATION AND POWER MANAGEMENT
CLOCK GENERATION AND POWER MANAGEMENT
Register Name Register Mnemonic Register Function
Power Save Register PWRSAV
Enables and sets clock division factor 0 F F 1
5.2.1.2Leaving Power-SaveMode
CLKOUT WR
CLOCK GENERATION AND POWER MANAGEMENT
Figure 5-10. Power-SaveClock Transition
CLOCK GENERATION AND POWER MANAGEMENT
Chip-SelectUnit
Page
6.1COMMON METHODS FOR GENERATING CHIP-SELECTS
6.2CHIP-SELECTUNIT FEATURES AND BENEFITS
CHAPTER CHIP-SELECTUNIT
CHIP-SELECTUNIT
6.3CHIP-SELECTUNIT FUNCTIONAL OVERVIEW
Chip-SelectsUsing
Chip-SelectsUsing
Internal
device EPROM or Flash memory types
1.The chip-selectis enabled
6.4.1Initialization Sequence
6.4PROGRAMMING
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
CHIP-SELECTUNIT
Register Name
Register Mnemonic
Register Function
Figure 6-9.MPCS Register Definition
MPCS
Register Mnemonic
CHIP-SELECTUNIT
6.4.2Programming the Active Ranges
Table 6-4.MCS Active Range
Table 6.3 LCS Active Range
CHIP-SELECTUNIT 6.4.2.2LCS Active Range
6.4.2.3MCS Active Range
Starting Address
Table 6-6.PCS Active Range
6.4.3Bus Wait State and Ready Control
CHIP-SELECTUNIT 6.4.2.4PCS Active Range
READY Wait State Ready
6.4.4Overlapping Chip-Selects
BUS READY R2 Control Bit Wait
Wait State Value R1:0 State Counter
6.4.6Programming Considerations
6.4.5Memory or I/O Bus Cycle Decoding
6.5CHIP-SELECTSAND BUS HOLD
6.6.1Example 1: Typical System Configuration
CSU Chip Select Device select
External Master Chip Select
Figure 6-13.Typical System
CHIP-SELECTUNIT
Example 6-1.Initializing the Chip-SelectUnit
CHIP-SELECTUNIT
CHIP-SELECTUNIT
Place memory variables here
CHIP-SELECTUNIT
Refresh Control Unit
Page
CHAPTER REFRESH CONTROL UNIT
7.3REFRESH CONTROL UNIT OPERATION
7.1THE ROLE OF THE REFRESH CONTROL UNIT
7.2REFRESH CONTROL UNIT CAPABILITIES
Refresh Control Unit Operation Set E Bit
Figure 7-3.Refresh Address Formation
7.4REFRESH ADDRESSES
REFRESH CONTROL UNIT
Table 7-1.Identification of Refresh Bus Cycles
7.5REFRESH BUS CYCLES
7.6GUIDELINES FOR DESIGNING DRAM CONTROLLERS
REFRESH CONTROL UNIT
T3/TW
REFRESH CONTROL UNIT
7.7PROGRAMMING THE REFRESH CONTROL UNIT
7.7.1Calculating the Refresh Interval
7.7.2Refresh Control Unit Registers
Register Mnemonic
RFBASE
Register Name:Refresh Base Address Register
Register Name
Refresh Clock Interval Register
RFTIME
Sets refresh rate
Controls Refresh Unit operation
7.7.3Programming Example
Register Name Register Mnemonic Register Function
Refresh Control Register RFCON
Example 7-1.Initializing the Refresh Control Unit
REFRESH CONTROL UNIT
REFRESH CONTROL UNIT
7.8REFRESH OPERATION AND BUS HOLD
CLKOUT
Page
Interrupt Control Unit
Page
8.1FUNCTIONAL OVERVIEW
CHAPTER INTERRUPT CONTROL UNIT
8.2.1Generic Functions in Master Mode
8.2MASTER MODE
Interrupt Name
Table 8-1.Default Interrupt Priorities
INTERRUPT CONTROL UNIT 8.2.1.1Interrupt Masking
8.2.1.2Interrupt Priority
8.2.1.3Interrupt Nesting
INTERRUPT CONTROL UNIT
8.3.1Typical Interrupt Sequence
8.3.2Priority Resolution
8.3FUNCTIONAL OPERATION IN MASTER MODE
•the Interrupt Control Unit has been initialized
8.3.2.2Interrupts That Share a Single Source
8.3.3Cascading with External 8259As
INTERRUPT CONTROL UNIT
INT0
Table 8-2.Fixed Interrupt Types
8.3.4Interrupt Acknowledge Sequence
8.3.5Polling
INTERRUPT CONTROL UNIT
8.3.7Additional Latency and Response Time
8.3.6Edge and Level Triggering
8.4PROGRAMMING THE INTERRUPT CONTROL UNIT
INTERRUPT CONTROL UNIT
8.4.1Interrupt Control Registers
Register Mnemonic: TCUCON, DMA0CON, DMA1CON
Register Mnemonic
I2CON, I3CON
INTERRUPT CONTROL UNIT
I0CON, I1CON
Register Mnemonic
Stores pending interrupt requests
8.4.2Interrupt Request Register
Interrupt Request Register
REQST
8.4.4Priority Mask Register
Interrupt Mask Register
IMASK
Masks individual interrupt sources
Register Mnemonic
8.4.5In-ServiceRegister
Register Name
Priority Mask Register
Register Mnemonic
8.4.6Poll and Poll Status Registers
Figure 8-10. In-ServiceRegister
Register Name
Figure 8-11.Poll Register
Register Name Register Mnemonic Register Function
Poll Register POLL
INTERRUPT CONTROL UNIT
Poll Status Register POLLSTS
8.4.7End-of-InterruptEOI Register
Read to check for pending interrupts when polling
Register Name Register Mnemonic Register Function
End-of-InterruptRegister EOI
8.4.8Interrupt Status Register
Used to issue an EOI command
Register Name Register Mnemonic Register Function
Interrupt Status Register INTSTS
8.5SLAVE MODE
Register Name Register Mnemonic Register Function
INTA
INT0 INTA 80186 Modular Core Select IRQ
8259A
82C59A
8.5.1Slave Mode Programming
Table 8-5.Slave Mode Fixed Interrupt Type Bits
INTERRUPT CONTROL UNIT
8.5.1.1Interrupt Vector Register
8.5.1.2End-Of-InterruptRegister
INTVEC
Register Mnemonic
INTERRUPT CONTROL UNIT
Register Mnemonic
Used to issue the EOI command
Register Name
End-of-InterruptRegister in Slave Mode
8.5.2Interrupt Vectoring in Slave Mode
Interrupt presented to Interrupt Control Unit
INTERRUPT CONTROL UNIT
Page
Timer/Counter Unit
Page
9.1FUNCTIONAL OVERVIEW
CHAPTER TIMER/COUNTER UNIT
T0 In
T1IN T0OUT T1OUT
TIMER/COUNTER UNIT
T0IN
Figure 9-3.Timers 0 and 1 Flow Chart
TIMER/COUNTER UNIT
Figure 9-3.Timers 0 and 1 Flow Chart Continued
TIMER/COUNTER UNIT
Dual Maximum Count Mode
9.2PROGRAMMING THE TIMER/COUNTER UNIT
Maxcount A
Maxcount B
Figure 9-5.Timer 0 and Timer 1 Control Registers
Timer 0 and 1 Control Registers T0CON, T1CON
Defines Timer 0 and 1 operation
TIMER/COUNTER UNIT
Register Name Register Mnemonic Register Function
TIMER/COUNTER UNIT
Figure 9-6.Timer 2 Control Register
Timer 2 Control Register T2CON
Defines Timer 2 operation
TIMER/COUNTER UNIT
TIMER/COUNTER UNIT
Timer Count Register
Contains the current timer count
T0CNT, T1CNT, T2CNT
9.2.1Initialization Sequence
Table 9-1.Timer 0 and 1 Clock Sources
9.2.2Clock Sources
9.2.3Counting Modes
TIMER/COUNTER UNIT
9.2.3.1Retriggering
TIMER/COUNTER UNIT
Table 9-2.Timer Retriggering
9.2.4Pulsed and Variable Duty Cycle Output
TIMER/COUNTER UNIT
Maxcount -
9.2.5Enabling/Disabling Counters
Timer Serviced 1
Internal Count Value
9.3TIMING
9.2.6Timer Interrupts
9.3.1Input Setup and Hold Timings
9.2.7Programming Considerations
9.3.5Digital One-Shot
9.3.2Synchronization and Maximum Frequency
9.3.3Real-TimeClock
9.3.4Square-WaveGenerator
Example 9-1.Configuring a Real-TimeClock
TIMER/COUNTER UNIT
TIMER/COUNTER UNIT
enable interrupts
TIMER/COUNTER UNIT
Example 9-2.Configuring a Square-WaveGenerator
TIMER/COUNTER UNIT
Example 9-3.Configuring a Digital One-Shot
TIMER/COUNTER UNIT
TIMER/COUNTER UNIT
Page
Direct Memory Access Unit
Page
10.1.1 The DMA Transfer
CHAPTER DIRECT MEMORY ACCESS UNIT
10.1 FUNCTIONAL OVERVIEW
Fetch
10.1.3 DMA Requests
10.1.2 Source and Destination Pointers
10.1.4 External Requests
Fetch Cycle
10.1.5 Internal Requests
10.1.5.1Timer 2-InitiatedTransfers
10.1.7.2Software Termination
10.1.6 DMA Transfer Counts
DIRECT MEMORY ACCESS UNIT
10.1.7.1Termination at Terminal Count
10.1.10 The Two-ChannelDMA Unit
10.1.8 DMA Unit Interrupts
10.1.9 DMA Cycles and the BIU
Module
10.2.1 DMA Channel Parameters
10.2 PROGRAMMING THE DMA UNIT
Register Mnemonic
DxSRCH
Register Name:DMA Source Address Pointer High
Register Mnemonic
DxSRCL
Register Name:DMA Source Address Pointer Low
Register Function
DIRECT MEMORY ACCESS UNIT
Register Mnemonic
DxDSTH
Register Mnemonic
DxDSTL
Register Name:DMA Destination Address Pointer Low
DIRECT MEMORY ACCESS UNIT
DMA Control Register
DxCON
Controls DMA channel parameters
Register Mnemonic
DIRECT MEMORY ACCESS UNIT
Register Name
DMA Control Register
DxCON
Register Name
DMA Control Register
Register Mnemonic
10.2.1.6Programming the Transfer Count Options
DIRECT MEMORY ACCESS UNIT
10.2.1.4Arming the DMA Channel
10.2.1.5Selecting Channel Synchronization
Register Name
DMA Transfer Count
DxTC
Contains the DMA channel’s transfer count
10.3.1 DRQ Pin Timing Requirements
10.2.2 Suspension of DMA Transfers
10.2.3 Initializing the DMA Unit
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT
10.3.3 DMA Transfer Rates
10.3.2 DMA Latency
10.4 DMA UNIT EXAMPLES
10.3.4 Generating a DMA Acknowledge
Example 10-1.Initializing the DMA Unit
DIRECT MEMORY ACCESS UNIT
Example 10-1.Initializing the DMA Unit Continued
DIRECT MEMORY ACCESS UNIT
SECTORS
DIRECT MEMORY ACCESS UNIT
Example 10-1.Initializing the DMA Unit Continued
Example 10-2.Timed DMA Transfers
DIRECT MEMORY ACCESS UNIT
Example 10-2.Timed DMA Transfers Continued
DIRECT MEMORY ACCESS UNIT
Page
Math Coprocessing
Page
11.2 AVAILABILITY OF MATH COPROCESSING
CHAPTER MATH COPROCESSING
11.1 OVERVIEW OF MATH COPROCESSING
11.3.1 80C187 Instruction Set
11.3 THE 80C187 MATH COPROCESSOR
•the 80C187 uses register or memory operands
Division
MATH COPROCESSING
Table 11-2.80C187 Arithmetic Instructions
Addition
Table 11-4.80C187 Transcendental Instructions
MATH COPROCESSING 11.3.1.3Comparison Instructions
Table 11-3.80C187 Comparison Instructions
11.3.1.4Transcendental Instructions
Table 11-6.80C187 Processor Control Instructions
MATH COPROCESSING 11.3.1.5Constant Instructions
Table 11-5.80C187 Constant Instructions
11.3.1.6Processor Control Instructions
11.4 MICROPROCESSOR AND COPROCESSOR OPERATION
11.3.2 80C187 Data Types
Figure 11-1. 80C187-SupportedData Types
MATH COPROCESSING
Core
MATH COPROCESSING
80C187
Modular
Table 11-7.80C187 I/O Port Assignments
11.4.2 Processor Bus Cycles Accessing the 80C187
11.4.1 Clocking the 80C187
MATH COPROCESSING
11.4.3 System Design Tips
Core
MATH COPROCESSING
80C187
Modular
11.5 EXAMPLE MATH COPROCESSOR ROUTINES
11.4.4 Exception Trapping
80C187
MATH COPROCESSING
80C186
Modular Core
MATH COPROCESSING
MATH COPROCESSING
ONCE Mode
Page
12.1 ENTERING/LEAVING ONCE MODE
CHAPTER ONCE MODE
All output
bidirectional weakly held pins except OSCOUT
ONCE MODE
Figure 12-1.Entering/Leaving ONCE Mode
80C186 Instruction Set Additions and Extensions
Page
PUSHA/POPA
A.1 80C186 INSTRUCTION SET ADDITIONS
A.1.1 Data Transfer Instructions
A.1.3 High-LevelInstructions
A.1.2 String Instructions
INS source_string, port
OUTS port, destination_string
1.Main has variables at fixed locations
Figure A-3.Stack Frame for Main at Level
Figure A-2.Variable Access in Nested Procedures
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
BP SP
BPA = BP Value for Procedure A
Figure A-4.Stack Frame for Procedure A at Level
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
Display B Dynamic Storage B
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
BP SP
Old BP BPM BPM BPM BPA BPA BPM BPA BPB
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
LEAVE
PUSH data
BOUND register, address
A.2 80C186 INSTRUCTION SET ENHANCEMENTS
A.2.1 Data Transfer Instructions
SAL destination, count
A.2.2 Arithmetic Instructions
IMUL destination, source, data
A.2.3 Bit Manipulation Instructions
RCR destination, count
ROL destination, count
ROR destination, count
RCL destination, count
Input Synchronization
Page
APPENDIX B INPUT SYNCHRONIZATION
B.1 WHY SYNCHRONIZERS ARE REQUIRED
B.2 ASYNCHRONOUS PINS
Instruction Set Descriptions
Page
Table C-1.Instruction Format Variables
APPENDIX C INSTRUCTION SET DESCRIPTIONS
Description
INSTRUCTION SET DESCRIPTIONS
Table C-2.Instruction Operands
Operand
Table C-3.Flag Bit Functions
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set
INSTRUCTION SET DESCRIPTIONS
ADC dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Description
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
Table C-4.Instruction Set Continued
Call Procedure
CALL procedure-name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
INSTRUCTION SET DESCRIPTIONS
Name
Clear Interrupt-enableFlag
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-10
C-11
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-12
Table C-4.Instruction Set Continued
When Source Operand is a Byte
When Source Operand is a Word
INSTRUCTION SET DESCRIPTIONS
C-14
Procedure Entry
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-15
Table C-4.Instruction Set Continued
When Source Operand is a Byte
When Source Operand is a Word
INSTRUCTION SET DESCRIPTIONS
IN accum, port
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-17
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-18
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-19
JA disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-20
JNB disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JAE disp8
JZ disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JE disp8
JGE disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JL disp8
JNZ disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JNE disp8
JP disp8
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
JO disp8
LDS dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-26
C-27
Load Pointer Using ES
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
LODS src-string
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-28
MOV dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-29
MOVS dest-string, src-string
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-30
C-31
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-32
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-33
C-34
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-35
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-36
C-37
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-38
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-39
SAL dest, count
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
SHL dest, count
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-41
Table C-4.Instruction Set Continued
When Source Operand is a Byte
When Source Operand is a Word
INSTRUCTION SET DESCRIPTIONS
SHR dest, src
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-43
STOS dest-string
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-44
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-45
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-46
Name
INSTRUCTION SET DESCRIPTIONS
Table C-4.Instruction Set Continued
C-47
Page
Instruction Set Opcodes and Clock Cycles
Page
Table D-1.Operand Variables
APPENDIX D INSTRUCTION SET OPCODES
AND CLOCK CYCLES
Format
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary
Function
ARITHMETIC INSTRUCTIONS
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
DATA TRANSFER INSTRUCTIONS Continued
ARITHMETIC INSTRUCTIONS Continued
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
BIT MANIPULATION INSTRUCTIONS
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
ARITHMETIC INSTRUCTIONS Continued
Shifts/Rotates
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
BIT MANIPULATION INSTRUCTIONS Continued
Table D-2.Instruction Set Summary Continued
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Iteration Control
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
PROGRAM TRANSFER INSTRUCTIONS Continued
Byte
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-2.Instruction Set Summary Continued
Table D-3.Machine Instruction Decoding Guide
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Bytes 3–6
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Byte
Byte
Table D-4.Mnemonic Encoding Matrix Left Half
INSTRUCTION SET OPCODES AND CLOCK CYCLES
D-21
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Table D-4.Mnemonic Encoding Matrix Right Half
Abbr
INSTRUCTION SET OPCODES AND CLOCK CYCLES
Abbr
Definition
Index
Page
ARDY, See READY Arithmetic
INDEX
Data bus, See Address and data bus
INDEX
Crystal‚ See Oscillator
Index-3
INDEX
See also Bus cycles
See also Refresh Control Unit
interrupt
INDEX
Index-4
Index-5
INDEX
Index-6
INDEX
Index-7
Timers‚ See Timer Counter Unit TCU
INDEX
Index-8
INDEX
