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80C186XL, 80C188XL user manual
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Contents
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CONTENTS
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TABLES
EXAMPLES
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CHAPTER 1 INTRODUCTION
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CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
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The arithmetic instructions (see Table 2-4) operate on four types of numbers:
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2-25
Table 2-9. Program Transfer Instructions
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Opcode Mod R/M EA
Displacement
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2-38
Figure 2-23. 80C186 Modular Core Family Supported Data Types
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2-40
Figure 2-25. Interrupt Vector Table
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CHAPTER 3 BUS INTERFACE UNIT
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!
3-19
BUS INTERFACE UNIT
Figure 3-18. Normally Ready System Timings
Conditions causing the BIU to become idle include the following.
!
tions).
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CLKOUT
DEN
RD,WR
DT/R
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CHAPTER 4 PERIPHERAL CONTROL BLOCK
PERIPHERAL CONTROL BLOCK
Figure 4-1. PCB Relocation Register
4-2
4-3
PERIPHERAL CONTROL BLOCK
Table 4-1. Peripheral Control Block
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CHAPTER 5 CLOCK GENERATION AND POWER MANAGEMENT
90 18090
Z = Inverter Output Z
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CLOCK GENERATION AND POWER MANAGEMENT
5-4
Figure 5-4. Equations for Crystal Calculations
Table 5-1. Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit
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CLKOUT WR
2
1
T2 T3 T4
CLOCK GENERATION AND POWER MANAGEMENT
Example 5-1. Initializing the Power Management Unit for Power-Save Mode
5-14
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CHAPTER 6 CHIP-SELECT UNIT
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6-7
Figure 6-5. UMCS Register Definition
6-8
Figure 6-6. LMCS Register Definition
6-9
Figure 6-7. MMCS Register Definition
6-10
Figure 6-8. PACS Register Definition
6-11
Figure 6-9. MPCS Register Definition
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Device select External Master Chip Select
CSU Chip Select
6-19
Figure 6-13. Typical System
6-20
Example 6-1. Initializing the Chip-Select Unit
6-21
Example 6-1. Initializing the Chip-Select Unit (Continued)
6-22
Example 6-1. Initializing the Chip-Select Unit (Continued)
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CHAPTER 7 REFRESH CONTROL UNIT
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7-9
Figure 7-7. Refresh Clock Interval Register 7.7.2.3 Refresh Control Register
7-10
Figure 7-8. Refresh Control Register
7-11
Example 7-1. Initializing the Refresh Control Unit
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CHAPTER 8 INTERRUPT CONTROL UNIT
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8-13
Figure 8-4. Interrupt Control Register for Internal Sources
8-14
Figure 8-5. Interrupt Control Register for Noncascadable External Pins
8-15
Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins
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8-17
Figure 8-8. Interrupt Mask Register
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8-19
Figure 8-10. In-Service Register
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8-26
8.5.1.1 Interrupt Vector Register
Table 8-4. Interrupt Control Unit Register Comparison
Table 8-5. Slave Mode Fixed Interrupt Type Bits
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8-28
Figure 8-18. End-of-Interrupt Register in Slave Mode 8.5.1.3 Other Registers
Figure 8-19. Request, Mask, and In-Service Registers
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8-31
Example 8-1. Initializing the Interrupt Control Unit for Master Mode
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CHAPTER 9 TIMER/COUNTER UNIT
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9-3
Figure 9-2. Counter Element Multiplexing and Timer Input Synchronization
T1IN T1OUT
T0IN
T0OUT
9-4
Figure 9-3. Timers 0 and 1 Flow Chart
9-5
Figure 9-3. Timers 0 and 1 Flow Chart (Continued)
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9-7
Figure 9-5. Timer 0 and Timer 1 Control Registers
9-8
Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)
9-9
Figure 9-6. Timer 2 Control Register
9-10
Figure 9-7. Timer Count Registers
9-11
Figure 9-8. Timer Maxcount Compare Registers
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9-18
Example 9-1. Configuring a Real-Time Clock
9-19
Example 9-1. Configuring a Real-Time Clock (Continued)
9-20
Example 9-1. Configuring a Real-Time Clock (Continued)
9-21
Example 9-2. Configuring a Square-Wave Generator
9-22
Example 9-2. Configuring a Square-Wave Generator (Continued)
Example 9-3. Configuring a Digital One-Shot
9-23
Example 9-3. Configuring a Digital One-Shot (Continued)
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CHAPTER 10 DIRECT MEMORY ACCESS UNIT
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10-12
Figure 10-8. DMA Source Pointer (Low-Order Bits)
10-13
Figure 10-9. DMA Destination Pointer (High-Order Bits)
10-14
10-15
Figure 10-11. DMA Control Register
10-16
Figure 10-11. DMA Control Register (Continued)
10-17
Figure 10-11. DMA Control Register (Continued) 10.2.1.3 Selecting the Source of DMA Requests
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10-19
Figure 10-12. Transfer Count Register
10.2.1.7 Generating Interrupts on Terminal Count
10.2.1.8 Setting the Relative Priority of a Channel
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10-23
Example 10-1. Initializing the DMA Unit
10-24
Example 10-1. Initializing the DMA Unit (Continued)
10-25
Example 10-1. Initializing the DMA Unit (Continued)
10-26
Example 10-2. Timed DMA Transfers
10-27
Example 10-2. Timed DMA Transfers (Continued)
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CHAPTER 11 MATH COPROCESSING
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11-4
Table 11-2. 80C187 Arithmetic Instructions
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CMD0
11-9
Figure 11-2. 80C186 Modular Core Family/80C187 System Configuration
CMD1
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x
11-15
Example 11-1. Initialization Sequence for 80C187 Math Coprocessor
11-16
Example 11-2. Floating Point Math Routine Using FSINCOS
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CHAPTER 12 ONCE MODE
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APPENDIX A 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
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APPENDIX B INPUT SYNCHRONIZATION
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C-1
APPENDIX C INSTRUCTION SET DESCRIPTIONS
Table C-1. Instruction Format Variables
C-2
Table C-2. Instruction Operands
C-3
Table C-3. Flag Bit Functions
C-4
Table C-4. Instruction Set
C-5
C-6
C-7
procedure-name
C-8
C-9
C-10
src-string
C-11
C-12
C-13
C-14
locals, levels
C-15
C-16
C-17
accum
port
C-18
dest-string, port
C-19
interrupt-type
C-20
C-21
C-22
C-23
target
C-24
C-25
C-26
C-27
C-28
src-string
C-29
C-30
dest-string, src-string
C-31
C-32
dest,src
port, accumulator
C-33
port, src_string
C-34
C-35
C-36
C-37
C-38
optional-pop-value
C-39
C-40
C-41
C-42
C-43
C-44
C-45
C-46
C-47
translate-table
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D-1
APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES
TTT
MMM
PPP
MMM
D-2
Table D-2. Instruction Set Summary
D-3
D-4
D-5
D-6
D-7
D-8
D-9
Table D-3. Machine Instruction Decoding Guide
D-10
D-11
D-12
D-13
D-14
D-15
D-16
D-17
D-18
D-19
D-20
Table D-4. Mnemonic Encoding Matrix (Left Half)
NOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.
Fx
Ex
D-21
Table D-4. Mnemonic Encoding Matrix (Right Half)
NOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.
x8 x9 xA xB xC xD xE xF
2x
D-22
Table D-5. Abbreviations for Mnemonic Encoding Matrix
Abbr Definition Abbr Definition Abbr Defini tion Abbr Definit ion
Byte 2 Immed Shift Grp1 Grp2
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INDEX
A
B
C
D
E
F
H
I
L
M
N
O
P
Q
R
S
T
W