Intel 80C186XL Instruction Set Descriptions, Table C-4.Instruction Set Continued, SHL dest, count

Models: 80C186XL 80C188XL

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SHL dest, count

INSTRUCTION SET DESCRIPTIONS

Table C-4. Instruction Set (Continued)

Name

Description

Operation

Flags

Affected

 

 

 

 

 

 

 

 

SHL

Shift Logical Left:

(temp) count

AF ?

SAL

Shift Arithmetic Left:

do while (temp) 0

CF

 

SHL dest, count

 

(CF) high-order bit of (dest)

DF –

 

 

(dest) (dest) × 2

IF –

 

SAL dest, count

 

 

 

(temp) (temp) – 1

OF

 

Shifts the destination byte or word left

 

if

PF

 

by the number of bits specified in the

 

count = 1

SF

 

count operand. Zeros are shifted in on

 

then

TF –

 

the right. If the sign bit retains its

 

if

ZF ¸

 

original value, then OF is cleared.

high-order bit of (dest) (CE)

 

 

Instruction Operands:

 

 

then

 

 

SHL reg, n

SAL reg, n

(OF) 1

 

 

SHL mem, n

SAL mem, n

else

 

 

SHL reg, CL

SAL reg, CL

(OF) 0

 

 

SHL mem, CL

SAL mem, CL

else

 

 

 

 

(OF) undefined

 

 

 

 

 

SAR

Shift Arithmetic Right:

(temp) count

AF ?

 

SAR dest, count

 

do while (temp) 0

CF

 

 

(CF) low-order bit of (dest)

DF –

 

Shifts the bits in the destination

 

(dest) (dest) / 2

IF –

 

operand (byte or word) to the right by

 

(temp) (temp) – 1

OF

 

the number of bits specified in the

 

if

PF

 

count operand. Bits equal to the

 

count = 1

SF

 

original high-order (sign) bit are shifted

 

then

TF –

 

in on the left, preserving the sign of the

 

if

ZF ¸

 

original value. Note that SAR does not

high-order bit of (dest)

 

 

produce the same result as the

 

 

next-to-high-order bit of (dest)

 

 

dividend of an "equivalent" IDIV

 

 

then

 

 

instruction if the destination operand is

 

 

(OF) 1

 

 

negative and 1 bits are shifted out. For

 

 

else

 

 

example, shifting –5 right by one bit

 

 

(OF) 0

 

 

yields –3, while integer division –5 by 2

 

 

else

 

 

yields –2. The difference in the instruc-

 

 

(OF) 0

 

 

tions is that IDIV truncates all numbers

 

 

 

 

 

toward zero, while SAR truncates

 

 

 

positive numbers toward zero and

 

 

 

negative numbers toward negative

 

 

 

infinity.

 

 

 

 

Instruction Operands:

 

 

 

SAR reg, n

 

 

 

 

SAR mem, n

 

 

 

 

SAR reg, CL

 

 

 

 

SAR mem, CL

 

 

 

 

 

 

 

 

NOTE: The three symbols used in the Flags Affected column are defined as follows:

the contents of the flag remain unchanged after the instruction is executed ¸? the contents of the flag is undefined after the instruction is executed

the flag is updated after the instruction is executed

C-40

Page 363
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Intel 80C186XL Instruction Set Descriptions, Table C-4.Instruction Set Continued, SHL dest, count, SAL dest, count