Intel 80C188XL, 80C186XL user manual Software Interrupts, Interrupt Latency

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

2.3.2Software Interrupts

A Software Interrupt is caused by executing an “INT n” instruction. The n parameter corresponds to the specific interrupt type to be executed. The interrupt type can be any number between 0 and

255.If the n parameter corresponds to an interrupt type associated with a hardware interrupt (NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in the Interrupt Status register are not altered.

The CPU processes software interrupts and exceptions in the same way. Software interrupts, ex- ceptions and traps cannot be masked.

2.3.3Interrupt Latency

Interrupt latency is the amount of time it takes for the CPU to recognize the existence of an inter- rupt. The CPU generally recognizes interrupts only between instructions or on instruction bound- aries. Therefore, the current instruction must finish executing before an interrupt can be recognized.

The worst-case 80C186 instruction execution time is an integer divide instruction with segment override prefix. The instruction takes 69 clocks, assuming an 80C186 Modular Core family mem- ber and a zero wait-state external bus. The execution time for an 80C188 Modular Core family member may be longer, depending on the queue.

This is one factor in determining interrupt latency. In addition, the following are also factors in determining maximum latency:

1.The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set.

2.The CPU does not recognize interrupts during HOLD.

3.Once communication is completely established with an 80C187, the CPU does not recognize interrupts until the numerics instruction is finished.

The CPU can recognize interrupts only on valid instruction boundaries. A valid instruction boundary usually occurs when the current instruction finishes. The following is a list of excep- tions:

1.MOVs and POPs referencing a segment register delay the servicing of interrupts until after the following instruction. The delay allows a 32-bit load to the SS and SP without an interrupt occurring between the two loads.

2.The CPU allows interrupts between repeated string instructions. If multiple prefixes precede a string instruction and the instruction is interrupted, only the one prefix preceding the string primitive is restored.

3.The CPU can be interrupted during a WAIT instruction. The CPU will return to the WAIT instruction.

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