Intel 80C188XL Contents, Chapter, Peripheral Control Block, Clock Generation And Power Management

						CONTENTS
CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1	PERIPHERAL CONTROL REGISTERS					4-1
4.2	PCB RELOCATION REGISTER					4-1
4.3	RESERVED LOCATIONS					4-4
4.4	ACCESSING THE PERIPHERAL CONTROL BLOCK					4-4
4.4.1		Bus Cycles				4-4
4.4.2 READY Signals and Wait States						4-4
4.4.3		F-Bus Operation				4-5
4.4.3.1		Writing the PCB Relocation Register				4-6
4.4.3.2		Accessing the Peripheral Control Registers				4-6
4.4.3.3		Accessing Reserved Locations				4-6
4.5	SETTING THE PCB BASE LOCATION					4-6
4.5.1 Considerations for the 80C187 Math Coprocessor Interface						4-7
CHAPTER 5
CLOCK GENERATION AND POWER MANAGEMENT
5.1	CLOCK GENERATION					5-1
5.1.1		Crystal Oscillator				5-1
5.1.1.1		Oscillator Operation				5-2
5.1.1.2		Selecting Crystals				5-5
5.1.2 Using an External Oscillator						5-6
5.1.3 Output from the Clock Generator						5-6
5.1.4 Reset and Clock Synchronization						5-6
5.2	POWER MANAGEMENT					5-10
5.2.1		Power-Save Mode				5-11
5.2.1.1		Entering Power-Save Mode				5-11
5.2.1.2		Leaving Power-Save Mode				5-13
5.2.1.3		Example Power-Save Initialization Code				5-13
CHAPTER 6
CHIP-SELECT UNIT
6.1	COMMON METHODS FOR GENERATING CHIP-SELECTS					6-1
6.2	CHIP-SELECT UNIT FEATURES AND BENEFITS					6-1
6.3	CHIP-SELECT UNIT FUNCTIONAL OVERVIEW					6-2
6.4	PROGRAMMING					6-6
6.4.1		Initialization Sequence				6-6
6.4.2 Programming the Active Ranges						6-12
6.4.2.1					Active Range	6-12
			UCS
6.4.2.2			LCS		.........................................................................................Active Range
6.4.2.3			MCS		........................................................................................Active Range
6.4.2.4			PCS	.........................................................................................Active Range
6.4.3 Bus Wait State and Ready Control						6-15
6.4.4		Overlapping Chip-Selects				6-16

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