Intel 80C188XL, 80C186XL user manual Entering Power-Save Mode

CLOCK GENERATION AND POWER MANAGEMENT

5.2.1Power-Save Mode

Power-Save mode is a means for reducing operating current. Power-Save mode enables a pro- grammable clock divider in the clock generation circuit.

NOTE

Power-Save mode can be used to stretch bus cycles as an alternative to wait states.

Possible clock divisor settings are 1 (undivided), 4, 8 and 16. The divided frequency feeds the core, the integrated peripherals and CLKOUT. The processor operates at the divided clock rate exactly as if the crystal or external oscillator frequency were lower by the same amount. Since the processor is static, a lower limit clock frequency does not apply. It may be necessary to repro- gram integrated peripherals such as the Timer Counter Unit and the Refresh Control Unit to com- pensate for the overall reduced clock rate.

5.2.1.1Entering Power-Save Mode

The Power-Save Register (Figure 5-9) controls Power-Save mode operation. The lower two bits select the divisor. When program execution sets the PSEN bit, the processor enters Power-Save mode. The internal clock frequency changes at the falling edge of T3 of the write to the Power- Save Register. CLKOUT changes simultaneously and does not glitch. Figure 5-10 illustrates the change at CLKOUT.

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