Intel 80C188XL, 80C186XL user manual DMA bus cycles

BUS INTERFACE UNIT

6.Internal error (e.g., divide error, overflow) interrupt vectoring sequence.

7.Hardware (e.g., INT0, DMA) interrupt vectoring sequence.

8.80C187 Math Coprocessor error interrupt vectoring sequence.

9.DMA bus cycles.

10.General instruction execution. This category includes read/write operations following a pipelined effective address calculation, vectoring sequences for software interrupts and numerics code execution. The following points apply to sequences of related execution cycles.

—The second read/write cycle of an odd-addressed word operation is inseparable from the first bus cycle.

—The second read/write cycle of an instruction with both load and store accesses (e.g., XCHG) can be separated from the first cycle by other bus cycles.

—Successive bus cycles of string instructions (e.g., MOVS) can be separated by other bus cycles.

—When a locked instruction begins, its associated bus cycles become the highest priority and cannot be separated (or preempted) until completed.

11.Bus cycles necessary to fill the prefetch queue.

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