Intel 80C186XL, 80C188XL 5.1.2Using an External Oscillator, 5.1.3Output from the Clock Generator

CLOCK GENERATION AND POWER MANAGEMENT

An important consideration when using crystals is that the oscillator start correctly over the volt- age and temperature ranges expected in operation. Observe oscillator startup in the laboratory. Varying the load capacitors (within about ± 50%) can optimize startup characteristics versus sta- bility. In your experiments, consider stray capacitance and scope loading effects.

For help in selecting external oscillator components for unusual circumstances, count on the crys- tal manufacturer as your best resource. Using low-cost ceramic resonators in place of crystals is possible if your application will tolerate less precise frequencies.

5.1.2Using an External Oscillator

The microprocessor’s on-board clock oscillator allows the use of a relatively low cost crystal. However, the designer may also use a “canned oscillator” or other external frequency source. Connect the external frequency input (EFI) signal directly to the oscillator X1 input. Leave X2 unconnected. This oscillator input drives the internal divide-by-two counter directly, generating the CPU clock signals. The external frequency input can have practically any duty cycle, provid- ed it meets the minimum high and low times stated in the data sheet. Selecting an external clock oscillator is more straightforward than selecting a crystal.

5.1.3Output from the Clock Generator

The crystal oscillator output drives a divide-by-two circuit, generating a 50% duty cycle clock for the processor’s integrated components. All processor timings refer to this clock, available exter- nally at the CLKOUT pin. CLKOUT changes state on the high-to-low transition of the X1 signal, even during reset and bus hold.

In a CMOS circuit, significant current flows only during logic level transitions. Since the micro- processor consists mostly of clocked circuitry, the clock distribution is the basis of power man- agement.

5.1.4Reset and Clock Synchronization

The clock generator provides a system reset signal (RESET). The RES input generates RESET and the clock generator synchronizes it to the CLKOUT signal.

A Schmitt trigger in the RES input ensures that the switch point for a low-to-high transition is greater than the switch point for a high-to-low transition. The processor must remain in reset a minimum of 4 CLKOUT cycles after VCC and CLKOUT stabilize. The hysteresis allows a simple

RC circuit to drive the RES input (see Figure 5-5). Typical applications can use about 100 milli- seconds as an RC time constant.

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