Intel 80C188XL, 80C186XL user manual Bus Interface Unit, Physical Address Generation

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE

The Execution Unit does not connect directly to the system bus. It obtains instructions from a queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Ad- dresses manipulated by the Execution Unit are 16 bits wide. The Bus Interface Unit, however, performs an address calculation that allows the Execution Unit to access the full megabyte of memory space.

To execute an instruction, the Execution Unit must first fetch the object code byte from the in- struction queue and then execute the instruction. If the queue is empty when the Execution Unit is ready to fetch an instruction byte, the Execution Unit waits for the Bus Interface Unit to fetch the instruction byte.

2.1.2Bus Interface Unit

The 80C186 Modular Core and 80C188 Modular Core Bus Interface Units are functionally iden- tical. They are implemented differently to match the structure and performance characteristics of their respective system buses. The Bus Interface Unit executes all external bus cycles. This unit consists of the segment registers, the Instruction Pointer, the instruction code queue and several miscellaneous registers. The Bus Interface Unit transfers data to and from the Execution Unit on the ALU data bus.

The Bus Interface Unit generates a 20-bit physical address in a dedicated adder. The adder shifts a 16-bit segment value left 4 bits and then adds a 16-bit offset. This offset is derived from com- binations of the pointer registers, the Instruction Pointer and immediate values (see Figure 2-2). Any carry from this addition is ignored.

			Shift left 4 bits			1	2	3	4
						15			0
1	2	3		4	0	0	0	2	2
19					0	15			0

+0 0 2 2

15 0

Segment Base

Logical

Address

Offset

=	1	2 3 6 2
	19		0
		To Memory

Physical Address

A1500-0A

Figure 2-2. Physical Address Generation

2-3