Clkout ALE, S20 Valid Status AD150 Address Data | Intel 80C186XL

BUS INTERFACE UNIT

T4	T1	T2	T3	T4
CLKOUT
ALE
S2:0	Valid	Status
AD15:0	Address		Data
RD / WR

A1507-0A

Figure 3-6. Typical Bus Cycle

		TN
	CLKOUT	Falling	Rising
	CLKOUT	Edge	Edge
		Edge	Edge
		Phase 1	Phase 2
		(Low Phase)	(High Phase)

A1111-0A

Figure 3-7. T-State Relation to CLKOUT

Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T- states labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pending. Multiple T3 states occur to generate wait states. The TW symbol represents a wait state.

The operation of a bus cycle can be separated into two phases:

•Address/Status Phase

•Data Phase

3-8

Image 89

Intel 80C186XL, 80C188XL user manual Clkout ALE, S20 Valid Status AD150 Address Data, Rd / Wr, Low Phase High Phase

Contents

80C186XL/80C188XL Microprocessor User’s Manual 80C186XL/80C188XL Microprocessor User’s Manual Intel Corporation Contents Contents Power Management Setting the PCB Base LocationClock Generation LCS Chapter Refresh Control Unit Functional Overview Functional Overview Programming the TIMER/COUNTER UnitProgramming the Interrupt Control Unit Chapter Math Coprocessing Chapter Once Mode Figures UCS Reset Configuration Interrupt Control Register for Noncascadable External Pins 10-9 Tables Flag Bit Functions Example Examples Introduction Page Chapter Introduction Comparison of 80C186 Modular Core Family Products HOW to USE this ManualFeature 80C186XL 80C186EA 80C186EB 80C186EC Document/Software Title Order No Related DocumentsRelated Documents and Software Electronic Support Systems FaxBack Service Bulletin Board System BBS Technical Support CompuServe ForumsWorld Wide Web Training Classes Product LiteraturePage Overview 80C186 Family Architecture Page Architectural Overview Chapter Overview of the 80C186 Family Architecture Execution Unit Simplified Functional Block Diagram of the 80C186 Family CPU Physical Address Generation Bus Interface Unit General Registers General Registers Operations Segment RegistersImplicit Use of General Registers Segment Registers Instruction Pointer Flags Memory Segmentation Register Mnemonic Register NamePSW Flags Register Function Segment Locations in Physical Memory Logical Addresses Fffffh Data DS Code CS Stack SS Extra ES 2BFH 2BEH 2BDH 2BCH 2BBH 2BAH Logical Address Sources Type of Memory Reference Default Alternate OffsetDynamically Relocatable Code Segment Data Extra Before After Relocation Code SegmentSegment Code Data Reserved Memory and I/O Space Stack Implementation 10. Stack Operation Instruction Set Software Overview Input/Output Data Transfer InstructionsGeneral-Purpose Sahf 7 6 5 4 3 2 1 Lahf S Z U a U P U CPushf Popf U U O D I T S Z U a U P U C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Subtraction AdditionMultiplication Division Bit Manipulation Instructions Arithmetic Interpretation of 8-Bit NumbersHex Bit Pattern Unsigned Signed Unpacked Packed Binary Shifts String Instructions CX AL/AX String Instruction Register and Flag UseProgram Transfer Instructions Overview of the 80C186 Family Architecture Unconditional Transfers Conditional TransfersIteration Control Interrupts Mnemonic Condition Tested Jump if… 10. Interpretation of Conditional Transfers Processor Control Instructions Addressing Modes11. Processor Control Instructions Register and Immediate Operand Addressing Modes Memory Addressing Modes BIU 0000 Physical Addr 13. Direct Addressing Opcode Mod R/M Displacement 15. Based Addressing 14. Register Indirect Addressing Rate Base Vac Displacement High Address Rate AgeBase Register Register Dept Div Employee Age 17. Indexed Addressing 18. Accessing an Array with Indexed Addressing 19. Based Index Addressing 20. Accessing a Stacked Array with Based Index Addressing Opcode Source EA Destination EA 12. Supported Data Types Data Types Used in the 80C186 Modular Core FamilyType Description BCD 23 C186 Modular Core Family Supported Data Types Interrupt/Exception Processing Interrupts and Exception Handling 3FC 3FE Overview of the 80C186 Family Architecture Stack Interrupt Enable BitPSW Trap Flag Exceptions Maskable Interrupts Invalid Opcode Type Interrupt Latency Software Interrupts Clocks Interrupt Response TimeTotal Interrupt and Exception Priority Iret Execute Divide Service RoutineNMI 29. Simultaneous NMI and Single Step Interrupts Trap Flag = ??? 30. Simultaneous NMI, Single Step and Maskable Interrupt Interrupt Enable Bit IE = Trap Flag TF =Page Bus Interface Unit Page 1 16-Bit Data Bus Multiplexed Address and Data BUSAddress and Data BUS Concepts MByte KBytes Physical Implementation Address Space forFffff Ffffe Ffffd Ffffc A190 D70 A191 D158 A191 D158 BHE High Even Byte TransferOdd Byte Transfer D70 A0 Low A191 D158 BHE High Bit Data Bus Even Word Transfers A191 D158 BHE Low D70 A0 Low A191 D158 BHE Low First Bus CycleSecond Bus Cycle D70 A0 High A191 D158 BHE Low Bit Data Bus Word Transfers Memory and I/O Interfaces BUS Cycle Operation 1 16-Bit Bus Memory and I/O Requirements2 8-Bit Bus Memory and I/O Requirements Low Phase High Phase PhaseClkout ALE S20 Valid Status AD150 Address Data Request Pending Bus ReadyHold Deasserted RES# Address/Status Phase Address Status Phase Or TW Or TI Data PhaseOr TI Clkout S20 A1916 ALE STB STB Wait States Data Phase AD150 Valid Write Data Read Read Data S20 Or TW Or TIClkout RD/ WR BUS Ready ReadyArdy Clkout Srdy CS1 CS2 CS3 CS4 ALE Clkout Clock 16. Generating a Normally Ready Bus Signal Idle States Clkout Ardy Srdy 18. Normally Ready System Timings Read Bus Cycles BUS CyclesRead Bus Cycle Types Read Cycle Critical Timing Parameters Rfsh A158A150 DT/R DEN AD70 O0-7 UCS27C256 LA151 AD158 Status Bits Bus Cycle Type A158 A150Write Bus Cycle Types LA0 BHE LA151A014 O18 CS1 AD70 AD158 LCS Write Cycle Critical Timing Parameters Interrupt Acknowledge Bus Cycle BHE RD, WR INTA0 INTA1Lock DT/R DEN System Design Considerations Processor 82C59AINTA0 Inta INT0 IR0 IR7 PCS0 LA1 Halt Bus Cycle 011 AD150 AD70 A158 A1916 Pins Pin StateRfsh = BHE Clkout Hold Hlda Temporarily Exiting the Halt Bus StateAD150 AD70 A158 A1916 Control BHE Rfsh S20 AD150 AD70 A158 A1916 T3 TI TI TI TI T4 T1 T2 T3AD70 A158 RFSH=1 System Design Alternatives NMI/INTx Clkout RD,WR DT/R DEN Buffering the Data Bus CPU Local Bus Buffered Bus DeviceDT/ R Buffer Buffered Data Bus AD70 MCS0Buffer Local Data Bus Synchronizing Software and Hardware Events Using a Locked Bus Queue Status Signal Decoding Using the Queue Status SignalsQueue Status No queue operation occurred Entering Bus Hold MULTI-MASTER BUS System Designs Float Signal Hold ConditionRD, W R Float BHE , S20 Lock Refresh Operation During a Bus Hold DT/R Lock Clkout Hold Hlda DEN RD, WRBHE, S20 Exiting Hold Hlda Reset Hold PRE CLRLatched Hlda BUS Cycle Priorities DEN RD, WR, BHEDT/R, S20 A1916, Lock BUS Interface Unit Page Peripheral Control Block Page PCB Relocation Register Peripheral Control Registers Relreg Bit Bit Name Reset Function Mnemonic StateRegister Name PCB Relocation Register Register Mnemonic Peripheral Control Block Ready Signals and Wait States Accessing the Peripheral Control BlockReserved Locations Bus Cycles Word reads Bus Operation Accessing the Peripheral Control Registers Setting the PCB Base LocationAccessing Reserved Locations Writing the PCB Relocation Register Considerations for the 80C187 Math Coprocessor Interface Page Clock Generation Power Management Page Crystal Oscillator Clock GenerationRES Oscillator Operation = Inverter Output Z 90˚ 180˚ Crystal Connections to Microprocessor Values µH Third-Overtone Crystal Inductor L1 Selecting Crystals Output from the Clock Generator Using an External OscillatorReset and Clock Synchronization 1µf typical Typical Ct = V 1 e Cold Reset Waveform Clkout PCS60,NCS RES Resync Clkout ResetPower Management Entering Power-Save Mode Power-Save Mode Enables and sets clock division factor Power Save RegisterRegister Name Register Mnemonic Register Function Pwrsav Example Power-Save Initialization Code 10. Power-Save Clock Transition Leaving Power-Save Mode Syntax Chip-Select Unit Page Common Methods for Generating CHIP-SELECTS CHIP-SELECT Unit Features and Benefits CHIP-SELECT Unit Functional Overview Chip-Selects Using Addresses Directly Simple Decoder27C256 74AC138 MCS2 MCS3MCS1 PCS1 MCS30, LCS A1916 UCS, PC S60 Srdy Ardy UCS 1AddressData Active For Top 1 KByte Memory Map 1MB Initialization Sequence ProgrammingChip-Select Unit Registers Control Register Alternate Register Controls the operation Chip-select UCS Control RegisterUmcs Lmcs LCS Control Register Mmcs MCS Control RegisterControls the operation Chip-selects MCS PCS PCS Control RegisterPacs X S Register NameMCS and PCS Alternate Control RegisterMpcs UCS Active Range Programming the Active RangesUCS Block Size and Starting Address Umcs Field Block Size Starting Address U1710 LCS Active Range LCS Active RangeMCS Active Range Lmcs Field Block Size Ending Address U1710 Block Size Mmcs Start Address Kbytes Restrictions MCS Block Size and Start Address Restrictions PCS Active Range Bus Wait State and Ready Control Overlapping Chip-Selects R2 Control Bit Wait Wait State Value R10 State CounterWait State Ready Programming Considerations Memory or I/O Bus Cycle Decoding Examples Example 1 Typical System ConfigurationCHIP-SELECTS and BUS Hold 13. Typical System MOD186XREF Name CSUEXAMPLE1 Example 6-1. Initializing the Chip-Select Unit Drambase EQU Place memory variables here Refresh Control Unit Page CLR REQ CPU Refresh Control Unit Operation Role of the Refresh Control UnitRefresh Control Unit Capabilities Refresh Control Unit Operation Flow Chart Refresh Address Formation Refresh Addresses Guidelines for Designing Dram Controllers Refresh BUS CyclesIdentification of Refresh Bus Cycles Data Bus Width RAS CAS T3/TW ClkoutMuxed Row Column Address S20 Refresh Control Unit Registers Programming the Refresh Control UnitCalculating the Refresh Interval Rfbase Register NameRefresh Base Address RegisterRegister FunctionDetermines upper 7 bits of refresh address Refresh Base Address Register Register Function Sets refresh rate Rftime Rfcon Refresh Control RegisterControls Refresh Unit operation Programming Example Example 7-1. Initializing the Refresh Control Unit Refresh Operation and BUS Hold RD, WR BHE, S2 DT / R A1916 Clkout Hold Hlda DENPage Interrupt Control Unit Page Functional Overview Chapter Interrupt Control Unit Timer 0 Timer 1 Timer Master ModeGeneric Functions in Master Mode DMA Interrupt Masking Default Interrupt PrioritiesInterrupt Priority Interrupt Name Relative Priority Interrupt Nesting Typical Interrupt Sequence Functional Operation in Master ModePriority Resolution Priority Resolution Example Interrupts That Share a Single Source Cascading with External 8259As Inta INTA0 INT INT0INT INT1 Inta INTA1 Polling Interrupt Acknowledge SequenceFixed Interrupt Types Interrupt Name Interrupt Type Additional Latency and Response Time Edge and Level Triggering Inta Idle Read IP Inta IdleRead CS Idle Push Flags Push CS Push IP Programming the Interrupt Control Unit 2AH Interrupt Control Registers2CH MSK Interrupt Control Register for Internal Sources LVL Register NameInterrupt Control Register non-cascadable pinsI2CON, I3CON I0CON, I1CON Register NameInterrupt Control Register cascadable pinsSfnm CAS Register Name Interrupt Request Register Register Mnemonic Interrupt Request RegisterReqst Register Function Stores pending interrupt requests Imask Register Name Interrupt Mask Register Register MnemonicRegister Function Masks individual interrupt sources Priority Mask Register Priority Mask Register In-Service RegisterPrimsk Masks lower-priority interrupt sources Inserv In-Service RegisterIndicates which interrupt handlers are in process Poll and Poll Status Registers Ireq Poll RegisterPoll Poll Status Register Read to check for pending interrupts when pollingPollsts End-of-Interrupt EOI Register End-of-Interrupt Register Used to issue an EOI commandEOI Interrupt Status Register Interrupt Status Register Slave ModeIntsts Dhlt IRQ INT VCC INT0 Inta 16. Interrupt Sources in Slave Mode Slave Mode Programming Master Mode Slave Mode PCB Offset Register Name Slave Mode Fixed Interrupt Type BitsInterrupt Vector Register Interrupt Control Unit Register Comparison Intvec Register NameInterrupt Vector Register Slave Mode only Used to issue the EOI command End-of-Interrupt Register in Slave Mode T1 T2 T3 T4 Interrupt Vectoring in Slave ModeInta INTA0 Select Lock CAS20 Slave Cascade Address From 8259A Inta Idle Read IP Read CS Push Flags Push CS Push IP Initializing the Interrupt Control Unit for Master Mode Priorities are used Page Timer/Counter Unit Page Chapter TIMER/COUNTER Unit Interrupt Latch Clock Timer Element Registers Output Latch T0IN T1IN T0OUT T1OUT Counter Element Multiplexing and Timer Input Synchronization Timers 0 and 1 Flow Chart From Timer/Counter Unit Output Modes Programming the TIMER/COUNTER Unit T0CON, T1CON Timer 0 and 1 Control RegistersDefines Timer 0 and 1 operation EXT RTGALT Cont Defines Timer 2 operation Timer 2 Control RegisterT2CON Maximum count. The MC bit must be cleared Register Function Contains the current timer count Register Name Timer Count Register Register MnemonicT0CNT, T1CNT, T2CNT C C Timer Maxcount Compare Registers Clock Sources Timer 0 and 1 Clock SourcesCounting Modes Clock Source Retriggering Pulsed and Variable Duty Cycle Output Timer RetriggeringTimer Operation Enabling/Disabling Counters Timer Serviced Internal Count Value Maxcount TxOUT Pin Timing Timer InterruptsInput Setup and Hold Timings Synchronization and Maximum Frequency Timer/Counter Unit Application ExamplesReal-Time Clock Square-Wave Generator Intsts Example 9-1. Configuring a Real-Time Clock Out Dx, al Timer2interruptroutine proc far T1CON Example 9-2. Configuring a Square-Wave Generator Example 9-3. Configuring a Digital One-Shot Cmpb Page Direct Memory Access Unit Page DMA Transfer Chapter Direct Memory Access Unit Typical DMA Transfer Fetch Deposit DMA Requests Source and Destination PointersDMA Transfer Directions Byte and Word Transfers T1 or T2 or T3 or TW or T4 or External RequestsCycle DRQ Source Synchronization DRQ Case Fetch Cycle Deposit Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TI Timer 2-Initiated TransfersClkout DRQ Case Termination and Suspension of DMA Transfers DMA Transfer Counts DMA Cycles and the BIU DMA Unit InterruptsTwo-Channel DMA Unit DMA Channel Arbitration Two-Channel DMA Module Module DMA Channel Parameters SRCProgramming the DMA Unit DMA Xxxxh Register NameDMA Source Address Pointer HighRegister Mnemonic DxSRCH S S a a Register NameDMA Source Address Pointer LowRegister Mnemonic DxSRCL Contains the upper 4 bits of the DMA Destination pointer Register NameDMA Destination Address Pointer HighDxDSTH Register Mnemonic DxDSTL Register NameDMA Destination Address Pointer Low Dmem D I E N C C C N TDdec Dinc Idrq Synchronization Type Word CHGStrt Programming the Transfer Count Options Arming the DMA ChannelSelecting Channel Synchronization Generating Interrupts on Terminal Count Setting the Relative Priority of a Channel Initializing the DMA Unit Suspension of DMA TransfersHardware Considerations and the DMA Unit DRQ Pin Timing Requirements DMA Transfer Rates DMA Latency DMA Unit Examples Generating a DMA Acknowledge MOV DS, AX Assume Dsdataseg Example 10-1. Initializing the DMA Unit 10-24 10-25 Example 10-2. Timed DMA Transfers 10-27 Page Math Coprocessing Page Availability of Math Coprocessing Overview of Math Coprocessing 11.3.1 80C187 Instruction Set 80C187 Math Coprocessor Real Transfers C187 Data Transfer InstructionsInteger Transfers Packed Decimal Transfers Other Operations C187 Arithmetic Instructions C187 Comparison Instructions Comparison InstructionsTranscendental Instructions C187 Transcendental Instructions C187 Constant Instructions Constant InstructionsC187 Processor Control Instructions Fldz FLD1 Fldpi FLDL2T FLDL2E FLDLG2 FLDLN2 Microprocessor and Coprocessor Operation 11.3.2 80C187 Data Types C187-Supported Data Types 80C186 80C187Modular Core Clocking the 80C187 Processor Bus Cycles Accessing the 80C187C187 I/O Port Assignments Address Read Definition Write Definition System Design Tips C187 Configuration with a Partially Buffered Bus Example Math Coprocessor Routines Exception Trapping C187 Exception Trapping via Processor Interrupt Pin 80C186 Modular Core Name Example80C187init Results Example 11-2. Floating Point Math Routine Using Fsincos Once Mode Page ENTERING/LEAVING Once Mode Chapter Once Mode Oscout RES UCS LCS 80C186 Instruction Set Additions Extensions Page Data Transfer Instructions 80C186 Instruction SET Additions High-Level Instructions String Instructions Figure A-1. Formal Definition of Enter Figure A-2. Variable Access in Nested Procedures Figure A-4. Stack Frame for Procedure a at Level BPM BPA BPB Leave 80C186 Instruction SET Enhancements Bound register, address Shift Instructions Arithmetic InstructionsBit Manipulation Instructions Rotate Instructions ROL destination, count Input Synchronization Page Figure B-1. Input Synchronization Circuit WHY Synchronizers are Required Asynchronous Pins Instruction Set Descriptions Page Variable Description Table C-1. Instruction Format Variables Operand Description Table C-2. Instruction Operands Table C-3. Flag Bit Functions Table C-4. Instruction Set AAS Ascii Adjust for SubtractionADC Add with Carry ADD dest, src ADDLogical Dest, src Call procedure-name Call ProcedureBound Detect Value Out of Range Clear Direction flag Convert Byte to WordClear Carry flag Complement Carry Flag Clear Interrupt-enable Flag Compare CMPCMP dest, src Compare String Convert Word to Doubleword Decimal Adjust for AdditionDecimal Adjust for Subtraction Decrement DEC When Source Operand is a Word Divide When Source Operand is a Byte Escape Procedure EntryEnter locals, levels Halt Integer Divide When Source Operand is a Byte Input Byte or Word When Source Operand is a Byte Integer Multiply When Source Operand is a ByteImul Accum, port Increment INCString INS dest-string, port INT interrupt-type Interrupt Interrupt Return Interrupt on OverflowJump on Above Jump on Not Below or Equal Jump on Not Below Jump on Above or EqualJump on Below Jump on Not Above or Equal Jump on Equal Jump on Zero Jump if CX ZeroJump on Greater Than Jump on Not Less Than or Equal Jump on Not Greater Than or Equal Name Description Operation Flags Affected Jump on Less ThanJump on Less Than or Equal Jump on Not Greater Than Jump on Not Zero Jump on Not EqualJump on Not Overflow Jump on Not Sign Jump on Parity Name Description Operation Flags Affected Jump on OverflowJump on Parity Equal Instruction Format LDS dest, src Load Pointer Using DSLoad Effective Address LEA dest, src Lock the Bus Load Pointer Using ESLES dest, src Lods src-string Load String Byte or Word When Source Operand is a ByteLoop Loop While Equal Loop While Not Zero Loop While Not EqualMove Byte or Word MOV dest, src Move String Multiply When Source Operand is a ByteMovs dest-string, src-string MUL NEG Negate When Source Operand is a ByteLogical Not When Source Operand is a Byte Or dest,src Name Description Operation Flags Affected Logical orOutput OUT port, accumulator Pop Out StringOuts port, srcstring Push Pop AllPop Flags Push Flags Push All RCL dest, count Rotate Through Carry LeftRotate Through Carry Right RCR dest, count Repeat While Equal RepeatRepeat While Zero Repeat While Not Equal Return RETRET optional-pop-value Rotate Left Store Register AH Into Flags Rotate RightROR dest, count Shift Arithmetic Right Shift Logical LeftShift Arithmetic Left SBB dest, src SBBSubtract With Borrow Scas dest-string Scan String When Source Operand is a Byte SHR dest, src Shift Logical RightSet Carry Flag Set Direction Flag Stos dest-string Set Interrupt-enable FlagStore Byte or Word String When Source Operand is a Byte Subtract SUBSUB dest, src Test Xchg dest, src WaitExchange Xlat translate-table TranslateExclusive Or XOR dest, srcPage Instruction Set Opcodes and Clock Cycles Page EA Calculation Table D-1. Operand VariablesMod Effect on EA Calculation Reg Bit w=1 Bit w=0 Function Format Clocks Table D-2. Instruction Set Summary Arithmetic Instructions Arithmetic Instructions BIT Manipulation Instructions String Manipulation Instructions JB/JNAE = LOOPNZ/LOOPNE = Processor Control Instructions Table D-3. Machine Instruction Decoding Guide Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AX,CX Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles Instruction SET Opcodes and Clock Cycles AL,DX Instruction SET Opcodes and Clock Cycles Table D-4. Mnemonic Encoding Matrix Left Half Table D-4. Mnemonic Encoding Matrix Right Half Abbr Definition Table D-5. Abbreviations for Mnemonic Encoding Matrix Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8